Re: [PATCH] perf/x86: Reset the counter to prevent the leak for a RDPMC task

[peterz]

On Thu, Jul 30, 2020 at 05:38:15AM -0700, kan.liang@xxxxxxxxxxxxxxx wrote:
> From: Kan Liang <kan.liang@xxxxxxxxxxxxxxx>
> 
> The counter value of a perf task may leak to another RDPMC task.

Sure, but nowhere did you explain why that is a problem.

> The RDPMC instruction is only available for the X86 platform. Only apply
> the fix for the X86 platform.

ARM64 can also do it, although I'm not sure what the current state of
things is here.

> After applying the patch,
> 
>     $ taskset -c 0 ./rdpmc_read_all_counters
>     index 0x0 value 0x0
>     index 0x1 value 0x0
>     index 0x2 value 0x0
>     index 0x3 value 0x0
> 
>     index 0x0 value 0x0
>     index 0x1 value 0x0
>     index 0x2 value 0x0
>     index 0x3 value 0x0

You forgot about:

 - telling us why it's a problem,
 - telling us how badly it affects performance.

I would feel much better if we only did this on context switches to
tasks that have RDPMC enabled.

So on del() mark the counter dirty (if we don't already have state that
implies this), but don't WRMSR. And then on
__perf_event_task_sched_in(), _after_ programming the new tasks'
counters, check for inactive dirty counters and wipe those -- IFF RDPMC
is on for that task.