[tip: x86/cpu] x86/split_lock: Enable the split lock feature on Sapphire Rapids and Alder Lake CPUs

[tip-bot2 for Fenghua Yu]

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     3aae57f0c3ba57715cf89201b5a5f290684078a5
Gitweb:        https://git.kernel.org/tip/3aae57f0c3ba57715cf89201b5a5f290684078a5
Author:        Fenghua Yu <fenghua.yu@xxxxxxxxx>
AuthorDate:    Fri, 24 Jul 2020 16:45:20 -07:00
Committer:     Ingo Molnar <mingo@xxxxxxxxxx>
CommitterDate: Sat, 25 Jul 2020 12:17:00 +02:00

x86/split_lock: Enable the split lock feature on Sapphire Rapids and Alder Lake CPUs

Add Sapphire Rapids and Alder Lake processors to CPU list to enumerate
and enable the split lock feature.

Signed-off-by: Fenghua Yu <fenghua.yu@xxxxxxxxx>
Signed-off-by: Ingo Molnar <mingo@xxxxxxxxxx>
Reviewed-by: Tony Luck <tony.luck@xxxxxxxxx>
Link: https://lore.kernel.org/r/1595634320-79689-1-git-send-email-fenghua.yu@xxxxxxxxx
---
 arch/x86/kernel/cpu/intel.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 0ab48f1..b6b7b38 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -1156,6 +1156,8 @@ static const struct x86_cpu_id split_lock_cpu_ids[] __initconst = {
 	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L,	1),
 	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L,		1),
 	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE,		1),
+	X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,	1),
+	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,		1),
 	{}
 };