Re: [PATCH] spi: dw-dma: Fix Tx DMA channel working too fast

[Andy Shevchenko]

On Tue, Jul 21, 2020 at 11:39 PM Serge Semin
<Sergey.Semin@xxxxxxxxxxxxxxxxxxxx> wrote:
>
> It turns out having a Rx DMA channel serviced with higher priority than
> a Tx DMA channel is not enough to provide a well balanced DMA-based SPI
> transfer interface. There might still be moments when the Tx DMA channel
> is occasionally handled faster than the Rx DMA channel. That in its turn
> will eventually cause the SPI Rx FIFO overflow if SPI bus speed is high
> enough to fill the SPI Rx FIFO in before it's cleared by the Rx DMA
> channel. That's why having the DMA-based SPI Tx interface too optimized
> is the errors prone, so the commit 0b2b66514fc9 ("spi: dw: Use DMA max
> burst to set the request thresholds") though being perfectly normal from
> the standard functionality point of view implicitly introduced the problem
> described above. In order to fix that the Tx DMA activity is intentionally
> slowed down by limiting the SPI Tx FIFO depth with a value twice bigger
> than the Tx burst length calculated earlier by the
> dw_spi_dma_maxburst_init() method.

Reviewed-by: Andy Shevchenko <andy.shevchenko@xxxxxxxxx>
Thanks!

> Fixes: 0b2b66514fc9 ("spi: dw: Use DMA max burst to set the request thresholds")
> Cc: Andy Shevchenko <andy.shevchenko@xxxxxxxxx>
> Cc: Alexey Malahov <Alexey.Malahov@xxxxxxxxxxxxxxxxxxxx>
> Cc: Feng Tang <feng.tang@xxxxxxxxx>
> Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx>
> ---
>  drivers/spi/spi-dw-dma.c | 14 +++++++++++++-
>  1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
> index 5986c520b196..bb390ff67d1d 100644
> --- a/drivers/spi/spi-dw-dma.c
> +++ b/drivers/spi/spi-dw-dma.c
> @@ -372,8 +372,20 @@ static int dw_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
>  {
>         u16 imr = 0, dma_ctrl = 0;
>
> +       /*
> +        * Having a Rx DMA channel serviced with higher priority than a Tx DMA
> +        * channel might not be enough to provide a well balanced DMA-based
> +        * SPI transfer interface. There might still be moments when the Tx DMA
> +        * channel is occasionally handled faster than the Rx DMA channel.
> +        * That in its turn will eventually cause the SPI Rx FIFO overflow if
> +        * SPI bus speed is high enough to fill the SPI Rx FIFO in before it's
> +        * cleared by the Rx DMA channel. In order to fix the problem the Tx
> +        * DMA activity is intentionally slowed down by limiting the SPI Tx
> +        * FIFO depth with a value twice bigger than the Tx burst length
> +        * calculated earlier by the dw_spi_dma_maxburst_init() method.
> +        */
>         dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1);
> -       dw_writel(dws, DW_SPI_DMATDLR, dws->fifo_len - dws->txburst);
> +       dw_writel(dws, DW_SPI_DMATDLR, dws->txburst);
>
>         if (xfer->tx_buf)
>                 dma_ctrl |= SPI_DMA_TDMAE;
> --
> 2.26.2
>


-- 
With Best Regards,
Andy Shevchenko