Re: [PATCH V3 09/16] arm64/cpufeature: Add remaining feature bits in ID_AA64ISAR0 register

[Anshuman Khandual]

On 05/05/2020 10:24 AM, Suzuki K Poulose wrote:
> On 05/02/2020 02:33 PM, Anshuman Khandual wrote:
>> Enable TLB features bit in ID_AA64ISAR0 register as per ARM DDI 0487F.a
>> specification.
>>
>> Cc: Catalin Marinas <catalin.marinas@xxxxxxx>
>> Cc: Will Deacon <will@xxxxxxxxxx>
>> Cc: Mark Rutland <mark.rutland@xxxxxxx>
>> Cc: Suzuki K Poulose <suzuki.poulose@xxxxxxx>
>> Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
>> Cc: linux-kernel@xxxxxxxxxxxxxxx
>>
>> Suggested-by: Will Deacon <will@xxxxxxxxxx>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@xxxxxxx>
>> ---
>> Â arch/arm64/include/asm/sysreg.h | 1 +
>>  arch/arm64/kernel/cpufeature.c | 1 +
>> Â 2 files changed, 2 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index 0f34927f52b9..40eaf89f1032 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -597,6 +597,7 @@
>> Â Â /* id_aa64isar0 */
>> Â #define ID_AA64ISAR0_RNDR_SHIFTÂÂÂÂÂÂÂ 60
>> +#define ID_AA64ISAR0_TLB_SHIFTÂÂÂÂÂÂÂ 56
>> Â #define ID_AA64ISAR0_TS_SHIFTÂÂÂÂÂÂÂ 52
>> Â #define ID_AA64ISAR0_FHM_SHIFTÂÂÂÂÂÂÂ 48
>> Â #define ID_AA64ISAR0_DP_SHIFTÂÂÂÂÂÂÂ 44
>> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>> index f4e15e355aee..dbedcae28061 100644
>> --- a/arch/arm64/kernel/cpufeature.c
>> +++ b/arch/arm64/kernel/cpufeature.c
>> @@ -174,6 +174,7 @@ static bool __system_matches_cap(unsigned int n);
>> ÂÂ */
>> Â static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
>> ÂÂÂÂÂ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
>> +ÂÂÂ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0),
> 
> I don't see any reason why this should be VISIBLE to the userspace.

Okay, will make it FTR_HIDDEN.