Re: MSI irqchip configured as IRQCHIP_ONESHOT_SAFE causes spurious IRQs

[Ramon Fried]

On Fri, Jan 17, 2020 at 7:11 PM Thomas Gleixner <tglx@xxxxxxxxxxxxx> wrote:
>
> Ramon,
>
> Ramon Fried <rfried.dev@xxxxxxxxx> writes:
> > On Fri, Jan 17, 2020 at 4:38 PM Thomas Gleixner <tglx@xxxxxxxxxxxxx> wrote:
> >> This is wrong. MSI is edge type, not level and you are really mixing up
> >> the concepts here.
> >>
> >> The fact that the MSI block raises a level interrupt on the output side
> >> has absolutely nothing to do with the type of the MSI interrupt itself.
> >>
> >> MSI is edge type by definition and this does not change just because
> >> there is a translation unit between the MSI interrupt and the CPU
> >> controller.
> >>
> >> The actual MSI interrupts do not even know about the existance of that
> >> MSI block at all. They do not care, as all they need to know is a
> >> message and an address. When an interrupt is raised in the device the
> >> MSI chip associated to the device (PCI or something else) writes this
> >> message to the address exactly ONCE. And this exactly ONCE defines the
> >> edge nature of MSI.
> >
> > OK, now I understand my mistake. thanks.
>
> :)
>
> >> A proper designed MSI device should not send another message before the
> >> interrupt handler which is associated to the device has handled the
> >> interrupt at the device level.
> >
> > By "MSI device" you mean the MSI controller in the SOC or the endpoint
> > that sends the MSI ?
>
> The device which incorporates the MSI endpoint.
This is not how the MSI specs describe it, so I'm confused.
According to spec, MSI is just an ordinary post PCIe TLP to a certain
memory on the root-complex.
The only information it has whether to send an MSI or not is the
masked/pending register in the config space.
So, basically, back to my original question, without tinkering with
these bits, the device will always send the MSI's,
it's just that they will be masked on the MSI controller on the host. right ?

Thanks,
Ramon.
>
> Thanks,
>
>         tglx