Re: [PATCH 5/9] dt-bindings: mmc: mmci: add delay block base register for sdmmc

[Ludovic BARRE]

Le 1/16/20 Ã 3:33 PM, Rob Herring a ÃcritÂ:
> On Thu, Jan 16, 2020 at 3:21 AM Ludovic BARRE <ludovic.barre@xxxxxx> wrote:
> > Hi Rob
> >
> > Le 1/15/20 Ã 3:56 PM, Rob Herring a Ãcrit :
> > > On Fri, Jan 10, 2020 at 02:48:19PM +0100, Ludovic Barre wrote:
> > > > To support the sdr104 mode, the sdmmc variant has a
> > > > hardware delay block to manage the clock phase when sampling
> > > > data received by the card.
> > > >
> > > > This patch adds a second base register (optional) for
> > > > sdmmc delay block.
> > > >
> > > > Signed-off-by: Ludovic Barre <ludovic.barre@xxxxxx>
> > > > ---
> > > >    Documentation/devicetree/bindings/mmc/mmci.txt | 2 ++
> > > >    1 file changed, 2 insertions(+)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/mmc/mmci.txt b/Documentation/devicetree/bindings/mmc/mmci.txt
> > > > index 6d3c626e017d..4ec921e4bf34 100644
> > > > --- a/Documentation/devicetree/bindings/mmc/mmci.txt
> > > > +++ b/Documentation/devicetree/bindings/mmc/mmci.txt
> > > > @@ -28,6 +28,8 @@ specific for ux500 variant:
> > > >    - st,sig-pin-fbclk       : feedback clock signal pin used.
> > > >
> > > >    specific for sdmmc variant:
> > > > +- reg                        : a second base register may be defined if a delay
> > > > +                           block is present and used for tuning.
> > >
> > > Which compatibles have a 2nd reg entry?
> >
> > In fact, mmci driver is ARM Amba driver (arm,primecell) and has only one
> > compatible "arm,pl18x".
> > The variants are identified by primecell-periphid property
> > (discovered at runtime with HW block register or defined by
> > device tree property "arm,primecell-periphid").
> >
> > The defaults "arm,pl18x" variants have only one base register,
> > but the SDMMC need a second base register for these
> > delay block registers.
> >
> > example of sdmmc node:
> >          sdmmc1: sdmmc@58005000 {
> >                  compatible = "arm,pl18x", "arm,primecell";
> >                  arm,primecell-periphid = <0x00253180>;
> >                  reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
> >          };
> >
> > what do you advise?
>
> I missed that this is a primecell block. Just give some indication
> which variants have this 2nd range.

Thanks Rob.
I will add primecell id(s) concerned by this 2nd range.

> 0
> Rob