Re: [PATCH] arm64: cpufeature: Enable Qualcomm Falkor errata 1009 for Kryo
From: Jeffrey Hugo
Date: Tue Oct 29 2019 - 11:08:00 EST
On 10/29/2019 7:44 AM, Jeffrey Hugo wrote:
On 10/29/2019 4:50 AM, Will Deacon wrote:
On Mon, Oct 28, 2019 at 11:06:04PM -0700, Bjorn Andersson wrote:
The Kryo cores share errata 1009 with Falkor, so add their model
definitions and enable it for them as well.
Signed-off-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
---
 arch/arm64/include/asm/cputype.h | 4 ++++
 arch/arm64/kernel/cpu_errata.c | 2 ++
 2 files changed, 6 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h
b/arch/arm64/include/asm/cputype.h
index b1454d117cd2..8067476ea2e4 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -84,6 +84,8 @@
 #define QCOM_CPU_PART_FALKOR_V1 0x800
 #define QCOM_CPU_PART_FALKOR 0xC00
 #define QCOM_CPU_PART_KRYO 0x200
+#define QCOM_CPU_PART_KRYO_GOLDÂÂÂÂÂÂÂ 0x211
+#define QCOM_CPU_PART_KRYO_SILVERÂÂÂ 0x205
These are not Kryo part numbers (8998+). They are Hydra ones.
Can you double-check this, please? My Pixel-1 phone claims something with
0x201, but I don't know if that's what you were aiming for. It would be
great if Qualcomm could document these register fields somewhere,
especially
since we're trying to work around their hardware errata for them.
I wish I could point you to public documentation. I don't happen to
know where it is. As far as 8996 goes, there are quite a few part
numbers. The ones I could find are:
201
205
211
241
251
281 happens to be QDF2432
From asking around, I found someone in the know. We don't have public
documentation, but I can follow up to try to create something - its
likely going to take a bit. I was given the following information to
share. This is specific to Hydra only-
MIDR[15:12] = PART[11:8]
Hydra and technology node differentiator (0x1 = Hydra 16nm; 0x2 = Hydra
14nm; 0x3 = Hydra 10nm)
MIDR[11:10] = PART[7:6]
This corresponds to the cluster revision number
MIDR[9:8] = PART[5:4]
Technology variant within the node
MIDR[7:6] = PART[3:2]
0b00 = 512KB L2
0b01 = 1MB L2
0b10 = 2MB L2
0b11 = 4MB L2
MIDR[5:4] = PART[1:0]
0b00 = uni-core
0b01 = dual-core cluster
0b10 = tri-core cluster
0b11 = quad-core cluster
That said...
 #define NVIDIA_CPU_PART_DENVER 0x003
 #define NVIDIA_CPU_PART_CARMEL 0x004
@@ -109,6 +111,8 @@
 #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM,
QCOM_CPU_PART_FALKOR_V1)
 #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM,
QCOM_CPU_PART_FALKOR)
 #define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM,
QCOM_CPU_PART_KRYO)
+#define MIDR_QCOM_KRYO_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM,
QCOM_CPU_PART_KRYO_GOLD)
+#define MIDR_QCOM_KRYO_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM,
QCOM_CPU_PART_KRYO_SILVER)
 #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA,
NVIDIA_CPU_PART_DENVER)
 #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA,
NVIDIA_CPU_PART_CARMEL)
 #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU,
FUJITSU_CPU_PART_A64FX)
diff --git a/arch/arm64/kernel/cpu_errata.c
b/arch/arm64/kernel/cpu_errata.c
index cdd8df033536..315780e7bee7 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -627,6 +627,8 @@ static const struct midr_range
arm64_harden_el2_vectors[] = {
 static const struct midr_range arm64_repeat_tlbi_cpus[] = {
 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
ÂÂÂÂÂ MIDR_RANGE(MIDR_QCOM_FALKOR_V1, 0, 0, 0, 0),
+ÂÂÂ MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_GOLD),
+ÂÂÂ MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_SILVER),
... why aren't you following what we do for E1003 and using the
'is_kryo_midr' callback to match these CPUs?
Will
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--
Jeffrey Hugo
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.