Re: [EXT] Re: [PATCH 2/3] ASoC: fsl_asrc: update supported sample format

[Nicolin Chen]

On Fri, Sep 13, 2019 at 05:48:40AM +0000, S.j. Wang wrote:
> Hi
> 
> > 
> > On Tue, Sep 10, 2019 at 02:07:25AM +0000, S.j. Wang wrote:
> > > > On Mon, Sep 09, 2019 at 06:33:20PM -0400, Shengjiu Wang wrote:
> > > > > The ASRC support 24bit/16bit/8bit input width, so S20_3LE format
> > > > > should not be supported, it is word width is 20bit.
> > > >
> > > > I thought 3LE used 24-bit physical width. And the driver assigns
> > > > ASRC_WIDTH_24_BIT to "width" for all non-16bit cases, so 20-bit
> > > > would go for that 24-bit slot also. I don't clearly recall if I had
> > > > explicitly tested S20_3LE, but I feel it should work since I put there...
> > >
> > > For S20_3LE, the width is 20bit,  but the ASRC only support 24bit, if
> > > set the ASRMCR1n.IWD= 24bit, because the actual width is 20 bit, the
> > > volume is Lower than expected,  it likes 24bit data right shift 4 bit.
> > > So it is not supported.
> > 
> > Hmm..S20_3LE right-aligns 20 bits in a 24-bit slot? I thought they're left
> > aligned...
> > 
> > If this is the case...shouldn't we have the same lower-volume problem for
> > all hardwares that support S20_3LE now?
> 
> Actually some hardware/module when they do transmission from FIFO
> to shift register, they can select the start bit, for example from the 20th
> bit. but not all module have this capability.
> 
> For ASRC, it haven't.  IWD can only cover the data width,  there is no
> Other bit for slot width.

Okay..let's drop the S20_3LE then. But would it be possible
for you to elaborate the reasoning into the commit message
also? Just for case when people ask why we remove it simply.

Thanks