Re: [PATCH] clk: socfpga: stratix10: fix rate caclulationg for cnt_clks

[Stephen Boyd]

Quoting Dinh Nguyen (2019-08-14 08:30:14)
> Checking bypass_reg is incorrect for calculating the cnt_clk rates.
> Instead we should be checking that there is a proper hardware register
> that holds the clock divider.
> 
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Dinh Nguyen <dinguyen@xxxxxxxxxx>
> ---

Applied to clk-fixes