Re: [PATCH v8 14/21] clk: tegra210: Add suspend and resume support

From: Sowjanya Komatineni
Date: Mon Aug 12 2019 - 13:28:26 EST


On 8/12/19 9:25 AM, Dmitry Osipenko wrote:
11.08.2019 22:15, Sowjanya Komatineni ÐÐÑÐÑ:
On 8/11/19 10:39 AM, Dmitry Osipenko wrote:
09.08.2019 21:40, Sowjanya Komatineni ÐÐÑÐÑ:
On 8/9/19 11:18 AM, Dmitry Osipenko wrote:
09.08.2019 19:19, Sowjanya Komatineni ÐÐÑÐÑ:
On 8/9/19 6:56 AM, Dmitry Osipenko wrote:
09.08.2019 2:46, Sowjanya Komatineni ÐÐÑÐÑ:
This patch adds support for clk: tegra210: suspend-resume.

All the CAR controller settings are lost on suspend when core
power goes off.

This patch has implementation for saving and restoring all PLLs
and clocks context during system suspend and resume to have the
clocks back to same state for normal operation.

Clock driver suspend and resume are registered as syscore_ops as clocks
restore need to happen before the other drivers resume to have all their
clocks back to the same state as before suspend.

Signed-off-by: Sowjanya Komatineni <skomatineni@xxxxxxxxxx>
---
ÂÂ drivers/clk/tegra/clk-tegra210.c | 103 +++++++++++++++++++++++++++++++++++++--
ÂÂ drivers/clk/tegra/clk.cÂÂÂÂÂÂÂÂÂ |Â 64 ++++++++++++++++++++++++
ÂÂ drivers/clk/tegra/clk.hÂÂÂÂÂÂÂÂÂ |ÂÂ 3 ++
ÂÂ 3 files changed, 166 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 998bf60b219a..8dd6f4f4debb 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -9,13 +9,13 @@
ÂÂ #include <linux/clkdev.h>
ÂÂ #include <linux/of.h>
ÂÂ #include <linux/of_address.h>
+#include <linux/syscore_ops.h>
ÂÂ #include <linux/delay.h>
ÂÂ #include <linux/export.h>
ÂÂ #include <linux/mutex.h>
ÂÂ #include <linux/clk/tegra.h>
ÂÂ #include <dt-bindings/clock/tegra210-car.h>
ÂÂ #include <dt-bindings/reset/tegra210-car.h>
-#include <linux/iopoll.h>
ÂÂ #include <linux/sizes.h>
ÂÂ #include <soc/tegra/pmc.h>
ÂÂ @@ -220,11 +220,15 @@
ÂÂ #define CLK_M_DIVISOR_SHIFT 2
ÂÂ #define CLK_M_DIVISOR_MASK 0x3
ÂÂ +#define CLK_MASK_ARMÂÂÂ 0x44
+#define MISC_CLK_ENBÂÂÂ 0x48
+
ÂÂ #define RST_DFLL_DVCO 0x2f4
ÂÂ #define DVFS_DFLL_RESET_SHIFT 0
ÂÂ Â #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8
ÂÂ #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac
+#define CPU_SOFTRST_CTRL 0x380
ÂÂ Â #define LVL2_CLK_GATE_OVRA 0xf8
ÂÂ #define LVL2_CLK_GATE_OVRC 0x3a0
@@ -2825,6 +2829,7 @@ static int tegra210_enable_pllu(void)
ÂÂÂÂÂÂ struct tegra_clk_pll_freq_table *fentry;
ÂÂÂÂÂÂ struct tegra_clk_pll pllu;
ÂÂÂÂÂÂ u32 reg;
+ÂÂÂ int ret;
ÂÂ ÂÂÂÂÂ for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) {
ÂÂÂÂÂÂÂÂÂÂ if (fentry->input_rate == pll_ref_freq)
@@ -2853,9 +2858,14 @@ static int tegra210_enable_pllu(void)
ÂÂÂÂÂÂ reg |= PLL_ENABLE;
ÂÂÂÂÂÂ writel(reg, clk_base + PLLU_BASE);
ÂÂ -ÂÂÂ readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg,
-ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ reg & PLL_BASE_LOCK, 2, 1000);
-ÂÂÂ if (!(reg & PLL_BASE_LOCK)) {
+ÂÂÂ /*
+ÂÂÂÂ * During clocks resume, same PLLU init and enable sequence get
+ÂÂÂÂ * executed. So, readx_poll_timeout_atomic can't be used here as it
+ÂÂÂÂ * uses ktime_get() and timekeeping resume doesn't happen by that
+ÂÂÂÂ * time. So, using tegra210_wait_for_mask for PLL LOCK.
+ÂÂÂÂ */
+ÂÂÂ ret = tegra210_wait_for_mask(&pllu, PLLU_BASE, PLL_BASE_LOCK);
+ÂÂÂ if (ret) {
ÂÂÂÂÂÂÂÂÂÂ pr_err("Timed out waiting for PLL_U to lock\n");
ÂÂÂÂÂÂÂÂÂÂ return -ETIMEDOUT;
ÂÂÂÂÂÂ }
@@ -3288,6 +3298,84 @@ static void tegra210_disable_cpu_clock(u32 cpu)
ÂÂ }
ÂÂ Â #ifdef CONFIG_PM_SLEEP
+/*
+ * This array lists mask values for each peripheral clk bank
+ * to mask out reserved bits during the clocks state restore
+ * on SC7 resume to prevent accidental writes to these reserved
+ * bits.
+ */
+static u32 periph_clk_rsvd_mask[TEGRA210_CAR_BANK_COUNT] = {
Should be more natural to have a "valid_mask" instead of "rsvd_mask".

What's actually wrong with touching of the reserved bits? They must be NO-OP.. or the
reserved bits are actually some kind of "secret" bits? If those bits have some use-case
outside of Silicon HW (like FPGA simulation), then this doesn't matter for upstream
and you
have to keep the workaround locally in the downstream kernel or whatever.
Will rename as valid_mask.

some bits in these registers are undefined and is not good to write to these bits as they
can cause pslverr.
Okay, it should be explained in the comment.

Is it possible to disable trapping of changing the undefined bits?
No its internal to design
Okay.

Also, what about to move the valid_mask into struct tegra_clk_periph_regs?
No, we cannot move to tegra_clk_periph_regs as its in tegra/clk.c and is common for all tegra.

Reserved bits are different on tegra chips so should come from Tegra chip specific clock
driver like

clk-tegra210 for Tegra210.
Could you please check whether the reserved bits are RAZ (read as zero)?

[snip]

yes all reserved bits of clk_enb register is 0. This should not be set to 1.

As I will be changing to variable name to valid_mask instead of reserved mask, will also change values to valid mask so it can be used directly to write to clk_enb for enabling all peripherals clks.