Re: [PATCH v8 05/21] clk: tegra: pll: Save and restore pll context
From: Sowjanya Komatineni
Date: Fri Aug 09 2019 - 14:50:41 EST
On 8/9/19 10:50 AM, Dmitry Osipenko wrote:
09.08.2019 20:39, Sowjanya Komatineni ÐÐÑÐÑ:
On 8/9/19 4:33 AM, Dmitry Osipenko wrote:
09.08.2019 2:46, Sowjanya Komatineni ÐÐÑÐÑ:
This patch implements save and restore of PLL context.
During system suspend, core power goes off and looses the settings
of the Tegra CAR controller registers.
So during suspend entry pll context is stored and on resume it is
restored back along with its state.
Acked-by: Thierry Reding <treding@xxxxxxxxxx>
Signed-off-by: Sowjanya Komatineni <skomatineni@xxxxxxxxxx>
---
 drivers/clk/tegra/clk-pll.c | 88 ++++++++++++++++++++++++++++-----------------
 drivers/clk/tegra/clk.h | 2 ++
 2 files changed, 58 insertions(+), 32 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 1583f5fc992f..e52add2bbdbb 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -1008,6 +1008,28 @@ static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
ÂÂÂÂÂ return rate;
 }
 +static void tegra_clk_pll_restore_context(struct clk_hw *hw)
+{
+ÂÂÂ struct tegra_clk_pll *pll = to_clk_pll(hw);
+ÂÂÂ struct clk_hw *parent = clk_hw_get_parent(hw);
+ÂÂÂ unsigned long parent_rate = clk_hw_get_rate(parent);
+ÂÂÂ unsigned long rate = clk_hw_get_rate(hw);
+ÂÂÂ u32 val;
+
+ÂÂÂ if (clk_pll_is_enabled(hw))
+ÂÂÂÂÂÂÂ return;
+
+ÂÂÂ if (pll->params->set_defaults)
+ÂÂÂÂÂÂÂ pll->params->set_defaults(pll);
+
+ÂÂÂ clk_pll_set_rate(hw, rate, parent_rate);
+
+ÂÂÂ if (!__clk_get_enable_count(hw->clk))
What about orphaned clocks? Is enable_count > 0 for them?
There are no orphaned pll clocks.
Sorry, I meant the "clk_ignore_unused".
clocks with CLK_IGNORE_UNUSED are taken care by clk driver.
clk_disable_unused checks for clocks with this flag and if they are not
enabled it will enable them.
So by the time suspend happens enable_count is > 0