Re: [PATCH 1/2 RESEND3] perf/x86/amd/uncore: Do not set ThreadMask and SliceMask for non-L3 PMCs

[Peter Zijlstra]

On Fri, Jun 28, 2019 at 09:59:20PM +0000, Phillips, Kim wrote:
> From: Kim Phillips <kim.phillips@xxxxxxx>
> 
> Commit d7cbbe49a930 ("perf/x86/amd/uncore: Set ThreadMask and SliceMask
> for L3 Cache perf events") enables L3 PMC events for all threads and
> slices by writing 1s in ChL3PmcCfg (L3 PMC PERF_CTL) register fields.
> 
> Those bitfields overlap with high order event select bits in the Data
> Fabric PMC control register, however.
> 
> So when a user requests raw Data Fabric events (-e amd_df/event=0xYYY/),
> the two highest order bits get inadvertently set, changing the counter
> select to events that don't exist, and for which no counts are read.
> 
> This patch changes the logic to write the L3 masks only when dealing
> with L3 PMC counters.
> 
> AMD Family 16h and below Northbridge (NB) counters were not affected.


Thanks!