[PATCH 2/4] ARM: dts: meson: switch to the generic Ethernet PHY reset bindings

From: Martin Blumenstingl
Date: Mon Jun 10 2019 - 12:42:27 EST

The snps,reset-gpio bindings are deprecated in favour of the generic
"Ethernet PHY reset" bindings.

Replace snps,reset-gpio from the &ethmac node with reset-gpios in the
ethernet-phy node. The old snps,reset-active-low property is now encoded
directly as GPIO flag inside the reset-gpios property.

snps,reset-delays-us is converted to reset-assert-us and
reset-deassert-us. reset-assert-us is the second cell from
snps,reset-delays-us while reset-deassert-us was the third cell.
Instead of blindly copying the old values (which seems strange since
they gave the PHY one second to come out of reset) over this also
updates the delays based on the datasheets:
- RTL8211F PHY on the Odroid-C1 and MXIII-Plus needs a 10ms delay (the
old settings used 10ms for assert and 1000ms for deassert)
- IP101GR PHY on the EC-100 and MXQ needs a 2.5ms delay (the old
settings used 10ms for assert and 1000ms for deassert)

No functional changes intended.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx>
---
arch/arm/boot/dts/meson8b-ec100.dts | 9 +++++----
arch/arm/boot/dts/meson8b-mxq.dts | 9 +++++----
arch/arm/boot/dts/meson8b-odroidc1.dts | 9 +++++----
arch/arm/boot/dts/meson8m2-mxiii-plus.dts | 8 ++++----
4 files changed, 19 insertions(+), 16 deletions(-)

diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts
index 9bf4249cb60d..e1d4fefa66c0 100644
--- a/arch/arm/boot/dts/meson8b-ec100.dts
+++ b/arch/arm/boot/dts/meson8b-ec100.dts
@@ -234,10 +234,6 @@
phy-handle = <&eth_phy0>;
phy-mode = "rmii";

- snps,reset-gpio = <&gpio GPIOH_4 0>;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-active-low;
-
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
@@ -246,6 +242,11 @@
eth_phy0: ethernet-phy@0 {
/* IC Plus IP101A/G (0x02430c54) */
reg = <0>;
+
+ reset-assert-us = <2500>;
+ reset-deassert-us = <2500>;
+ reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
+
icplus,select-interrupt;
interrupt-parent = <&gpio_intc>;
/* GPIOH_3 */
diff --git a/arch/arm/boot/dts/meson8b-mxq.dts b/arch/arm/boot/dts/meson8b-mxq.dts
index ef602ab45efd..790441bdffa9 100644
--- a/arch/arm/boot/dts/meson8b-mxq.dts
+++ b/arch/arm/boot/dts/meson8b-mxq.dts
@@ -91,10 +91,6 @@
phy-handle = <&eth_phy0>;
phy-mode = "rmii";

- snps,reset-gpio = <&gpio GPIOH_4 0>;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-active-low;
-
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
@@ -103,6 +99,11 @@
eth_phy0: ethernet-phy@0 {
/* IC Plus IP101A/G (0x02430c54) */
reg = <0>;
+
+ reset-assert-us = <2500>;
+ reset-deassert-us = <2500>;
+ reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
+
icplus,select-interrupt;
interrupt-parent = <&gpio_intc>;
/* GPIOH_3 */
diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts
index 018695b2b83a..c41dbb7acc56 100644
--- a/arch/arm/boot/dts/meson8b-odroidc1.dts
+++ b/arch/arm/boot/dts/meson8b-odroidc1.dts
@@ -176,10 +176,6 @@
&ethmac {
status = "okay";

- snps,reset-gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 30000>;
-
pinctrl-0 = <&eth_rgmii_pins>;
pinctrl-names = "default";

@@ -195,6 +191,11 @@
/* Realtek RTL8211F (0x001cc916) */
eth_phy: ethernet-phy@0 {
reg = <0>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <10000>;
+ reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
+
interrupt-parent = <&gpio_intc>;
/* GPIOH_3 */
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
diff --git a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts
index 59b07a55e461..46eb656a128f 100644
--- a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts
+++ b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts
@@ -73,10 +73,6 @@

amlogic,tx-delay-ns = <4>;

- snps,reset-gpio = <&gpio GPIOH_4 0>;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-active-low;
-
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
@@ -85,6 +81,10 @@
eth_phy0: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <10000>;
+ reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
};
};
};
--
2.22.0