Re: [PATCH v3 05/11] PCI: dwc: imx6: Share PHY debug register definitions

[Lucas Stach]

Am Sonntag, den 31.03.2019, 21:25 -0700 schrieb Andrey Smirnov:
> Both pcie-designware.c and pci-imx6.c contain custom definitions for
> PHY debug registers R0/R1 and on top of that there's already a
> definition for R0 in pcie-designware.h. Move all of the definitions to
> pcie-designware.h. No functional change intended.
> 
> > Cc: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>
> > Cc: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
> > Cc: Fabio Estevam <fabio.estevam@xxxxxxx>
> > Cc: Chris Healy <cphealy@xxxxxxxxx>
> > Cc: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
> > Cc: Leonard Crestez <leonard.crestez@xxxxxxx>
> > Cc: "A.s. Dong" <aisheng.dong@xxxxxxx>
> > Cc: Richard Zhu <hongxing.zhu@xxxxxxx>
> Cc: linux-imx@xxxxxxx
> Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
> Cc: linux-kernel@xxxxxxxxxxxxxxx
> Cc: linux-pci@xxxxxxxxxxxxxxx
> Signed-off-by: Andrey Smirnov <andrew.smirnov@xxxxxxxxx>

Reviewed-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>

> ---
> Âdrivers/pci/controller/dwc/pci-imx6.cÂÂÂÂÂÂÂÂ|ÂÂ6 ++----
> Âdrivers/pci/controller/dwc/pcie-designware.c | 12 +++---------
> Âdrivers/pci/controller/dwc/pcie-designware.h |ÂÂ3 +++
> Â3 files changed, 8 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 92c40c250a34..bb95a3273ca2 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -103,8 +103,6 @@ struct imx6_pcie {
> Â
> Â/* PCIe Port Logic registers (memory-mapped) */
> Â#define PL_OFFSET 0x700
> -#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
> -#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
> Â
> Â#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
> Â#define PCIE_PHY_CTRL_DATA_LOC 0
> @@ -839,8 +837,8 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
> Â
> Âerr_reset_phy:
> > Â	dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
> > -		dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
> > -		dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
> > +		dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0),
> > +		dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1));
> > Â	imx6_pcie_reset_phy(imx6_pcie);
> > Â	return ret;
> Â}
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 31f6331ca46f..086e87a40316 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -14,12 +14,6 @@
> Â
> Â#include "pcie-designware.h"
> Â
> -/* PCIe Port Logic registers */
> > -#define PLR_OFFSET			0x700
> > -#define PCIE_PHY_DEBUG_R1		(PLR_OFFSET + 0x2c)
> > -#define PCIE_PHY_DEBUG_R1_LINK_UP	(0x1 << 4)
> > -#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING	(0x1 << 29)
> -
> Âint dw_pcie_read(void __iomem *addr, int size, u32 *val)
> Â{
> > Â	if (!IS_ALIGNED((uintptr_t)addr, size)) {
> @@ -334,9 +328,9 @@ int dw_pcie_link_up(struct dw_pcie *pci)
> > Â	if (pci->ops->link_up)
> > Â		return pci->ops->link_up(pci);
> Â
> > -	val = readl(pci->dbi_base + PCIE_PHY_DEBUG_R1);
> > -	return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) &&
> > -		(!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
> > +	val = readl(pci->dbi_base + PCIE_PORT_DEBUG1);
> > +	return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
> > +		(!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
> Â}
> Â
> Âvoid dw_pcie_setup(struct dw_pcie *pci)
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 377f4c0b52da..662bb9082c76 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -41,6 +41,9 @@
> > Â#define PCIE_PORT_DEBUG0		0x728
> > Â#define PORT_LOGIC_LTSSM_STATE_MASK	0x1f
> > Â#define PORT_LOGIC_LTSSM_STATE_L0	0x11
> > +#define PCIE_PORT_DEBUG1		0x72C
> > +#define PCIE_PORT_DEBUG1_LINK_UP		(0x1 << 4)
> > +#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING	(0x1 << 29)
> Â
> > Â#define PCIE_LINK_WIDTH_SPEED_CONTROL	0x80C
> > Â#define PORT_LOGIC_SPEED_CHANGE		BIT(17)