Re: [PATCH v5 3/9] clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data

[Stephen Boyd]

Quoting Weiyi Lu (2019-03-04 21:05:40)
> From: Owen Chen <owen.chen@xxxxxxxxxxxx>
> 
> 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits,
>    add a variable to indicate this change and
>    backward-compatible.
> 2. fmin: The pll freqency lower-bound is vary from 1GMhz to
>    1.5Ghz, add a variable to indicate platform-dependent.
> 
> Signed-off-by: Owen Chen <owen.chen@xxxxxxxxxxxx>
> Signed-off-by: Weiyi Lu <weiyi.lu@xxxxxxxxxxxx>
> Acked-by: Sean Wang <sean.wang@xxxxxxxxxx>
> ---

Applied to clk-next