Re: [PATCH 2/2] perf/x86/intel: Add Tremont core PMU support

[Liang, Kan]

On 4/10/2019 3:51 AM, Peter Zijlstra wrote:
> On Tue, Apr 09, 2019 at 06:10:00PM -0700, kan.liang@xxxxxxxxxxxxxxx wrote:
>
> > The generic purpose counter 0 and fixed counter 0 have less skid.
> > Force :ppp events on generic purpose counter 0.
> > Force instruction:ppp always on fixed counter 0.
>
> > +static struct event_constraint *
> > +tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
> > +			  struct perf_event *event)
> > +{
> > +	struct event_constraint *c;
> > +
> > +	/*
> > +	 * :ppp means to do reduced skid PEBS,
> > +	 * which is available at PMC0 and fixed counter 0.
> > +	 */
> > +	if (event->attr.precise_ip == 3) {
> > +		/* Force instruction:ppp in Fixed counter 0 */
> > +		if (event->hw.config == X86_CONFIG(.event=0xc0))
> > +			return &fixed_counter0_constraint;
> > +
> > +		return &counter0_constraint;
>
> I'm confused, 0xc0 is the architectural 'instructions' event, surely we
> can program that on pmc0 too?
>
> Did we want a fixed0_counter0_constraint for that?

Yes, I will send out V2 shortly to fix it.

Thanks,
Kan