RE: [PATCH v2] RISC-V: Implement ASID allocator

[Anup Patel]

> -----Original Message-----
> From: Guo Ren <guoren@xxxxxxxxxx>
> Sent: Tuesday, April 9, 2019 8:33 AM
> To: Anup Patel <Anup.Patel@xxxxxxx>
> Cc: Palmer Dabbelt <palmer@xxxxxxxxxx>; Albert Ou
> <aou@xxxxxxxxxxxxxxxxx>; linux-kernel@xxxxxxxxxxxxxxx; Mike Rapoport
> <rppt@xxxxxxxxxxxxx>; Christoph Hellwig <hch@xxxxxxxxxxxxx>; Atish Patra
> <Atish.Patra@xxxxxxx>; Gary Guo <gary@xxxxxxxxxxx>; Paul Walmsley
> <paul.walmsley@xxxxxxxxxx>; linux-riscv@xxxxxxxxxxxxxxxxxxx
> Subject: Re: [PATCH v2] RISC-V: Implement ASID allocator
> 
> Hi Anup,
> 
> On Thu, Mar 28, 2019 at 06:32:36AM +0000, Anup Patel wrote:
> > This patch is tested on QEMU/virt machine and SiFive Unleashed board.
> > On QEMU/virt machine, we see 10% (approx) performance improvement
> with
> > SW emulated TLBs provided by QEMU. Unfortunately, ASID bits of SATP
> > CSR are not implemented on SiFive Unleashed board so we don't see any
> > change in performance.
> Can you tell me what is the test case ?

I am testing this using hackbench.

Regards,
Anup