Re: [PATCH v4 1/2] dmaengine: 8250_mtk_dma: add Mediatek uart DMA support

[kbuild test robot]

Hi Long,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on linus/master]
[also build test ERROR on v4.20-rc6 next-20181207]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Long-Cheng/add-uart-DMA-function/20181210-125624
config: s390-allmodconfig (attached as .config)
compiler: s390x-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        GCC_VERSION=7.2.0 make.cross ARCH=s390 

All error/warnings (new ones prefixed by >>):

>> drivers/dma/mediatek/8250_mtk_dma.c:29:30: error: 'CONFIG_SERIAL_8250_NR_UARTS' undeclared here (not in a function); did you mean 'CONFIG_SERIAL_RP2_NR_UARTS'?
    #define MTK_APDMA_CHANNELS  (CONFIG_SERIAL_8250_NR_UARTS * 2)
                                 ^
>> drivers/dma/mediatek/8250_mtk_dma.c:75:25: note: in expansion of macro 'MTK_APDMA_CHANNELS'
     void __iomem *mem_base[MTK_APDMA_CHANNELS];
                            ^~~~~~~~~~~~~~~~~~

vim +29 drivers/dma/mediatek/8250_mtk_dma.c

    27	
    28	#define MTK_APDMA_DEFAULT_REQUESTS	127
  > 29	#define MTK_APDMA_CHANNELS		(CONFIG_SERIAL_8250_NR_UARTS * 2)
    30	
    31	#define VFF_EN_B		BIT(0)
    32	#define VFF_STOP_B		BIT(0)
    33	#define VFF_FLUSH_B		BIT(0)
    34	#define VFF_4G_SUPPORT_B	BIT(0)
    35	#define VFF_RX_INT_EN0_B	BIT(0)	/*rx valid size >=  vff thre*/
    36	#define VFF_RX_INT_EN1_B	BIT(1)
    37	#define VFF_TX_INT_EN_B		BIT(0)	/*tx left size >= vff thre*/
    38	#define VFF_WARM_RST_B		BIT(0)
    39	#define VFF_RX_INT_FLAG_CLR_B	(BIT(0) | BIT(1))
    40	#define VFF_TX_INT_FLAG_CLR_B	0
    41	#define VFF_STOP_CLR_B		0
    42	#define VFF_FLUSH_CLR_B		0
    43	#define VFF_INT_EN_CLR_B	0
    44	#define VFF_4G_SUPPORT_CLR_B	0
    45	
    46	/* interrupt trigger level for tx */
    47	#define VFF_TX_THRE(n)		((n) * 7 / 8)
    48	/* interrupt trigger level for rx */
    49	#define VFF_RX_THRE(n)		((n) * 3 / 4)
    50	
    51	#define MTK_DMA_RING_SIZE	0xffffU
    52	/* invert this bit when wrap ring head again*/
    53	#define MTK_DMA_RING_WRAP	0x10000U
    54	
    55	#define VFF_INT_FLAG		0x00
    56	#define VFF_INT_EN		0x04
    57	#define VFF_EN			0x08
    58	#define VFF_RST			0x0c
    59	#define VFF_STOP		0x10
    60	#define VFF_FLUSH		0x14
    61	#define VFF_ADDR		0x1c
    62	#define VFF_LEN			0x24
    63	#define VFF_THRE		0x28
    64	#define VFF_WPT			0x2c
    65	#define VFF_RPT			0x30
    66	/*TX: the buffer size HW can read. RX: the buffer size SW can read.*/
    67	#define VFF_VALID_SIZE		0x3c
    68	/*TX: the buffer size SW can write. RX: the buffer size HW can write.*/
    69	#define VFF_LEFT_SIZE		0x40
    70	#define VFF_DEBUG_STATUS	0x50
    71	#define VFF_4G_SUPPORT		0x54
    72	
    73	struct mtk_dmadev {
    74		struct dma_device ddev;
  > 75		void __iomem *mem_base[MTK_APDMA_CHANNELS];
    76		spinlock_t lock; /* dma dev lock */
    77		struct tasklet_struct task;
    78		struct list_head pending;
    79		struct clk *clk;
    80		unsigned int dma_requests;
    81		bool support_33bits;
    82		unsigned int dma_irq[MTK_APDMA_CHANNELS];
    83		struct mtk_chan *ch[MTK_APDMA_CHANNELS];
    84	};
    85	

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0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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