Re: [PATCH v2 3/3] PCI: imx: Add support for i.MX8MQ

From: Lucas Stach
Date: Thu Dec 06 2018 - 05:23:58 EST

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Am Mittwoch, den 05.12.2018, 23:35 -0800 schrieb Andrey Smirnov:
> Add code needed to support i.MX8MQ variant.
>
> Cc: bhelgaas@xxxxxxxxxx
> > Cc: Fabio Estevam <fabio.estevam@xxxxxxx>
> Cc: cphealy@xxxxxxxxx
> Cc: l.stach@xxxxxxxxxxxxxx
> > Cc: Leonard Crestez <leonard.crestez@xxxxxxx>
> > Cc: "A.s. Dong" <aisheng.dong@xxxxxxx>
> > Cc: Richard Zhu <hongxing.zhu@xxxxxxx>
> Cc: linux-imx@xxxxxxx
> Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
> Cc: linux-kernel@xxxxxxxxxxxxxxx
> Cc: linux-pci@xxxxxxxxxxxxxxx
> > Cc: Mark Rutland <mark.rutland@xxxxxxx>
> > Cc: Rob Herring <robh@xxxxxxxxxx>
> Cc: devicetree@xxxxxxxxxxxxxxx
> Signed-off-by: Andrey Smirnov <andrew.smirnov@xxxxxxxxx>

Reviewed-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>

> ---
> Â.../bindings/pci/fsl,imx6q-pcie.txtÂÂÂÂÂÂÂÂÂÂÂ|ÂÂ6 +-
> Âdrivers/pci/controller/dwc/KconfigÂÂÂÂÂÂÂÂÂÂÂÂ|ÂÂ2 +-
> Âdrivers/pci/controller/dwc/pci-imx6.cÂÂÂÂÂÂÂÂÂ| 85 +++++++++++++++++--
> Â3 files changed, 86 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> index f37494d5a7be..40b46d11e7e7 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> @@ -9,6 +9,7 @@ Required properties:
> > Â - "fsl,imx6sx-pcie",
> > Â - "fsl,imx6qp-pcie"
> > Â - "fsl,imx7d-pcie"
> > + - "fsl,imx8mq-pcie"
> Â- reg: base address and length of the PCIe controller
> Â- interrupts: A list of interrupt outputs of the controller. Must contain an
> ÂÂÂentry for each entry in the interrupt-names property.
> @@ -43,7 +44,7 @@ Additional required properties for imx6sx-pcie:
> > Â - "pcie_inbound_axi"
> Â- power-domains: Must be set to a phandle pointing to the PCIE_PHY power domain
> Â
> -Additional required properties for imx7d-pcie:
> +Additional required properties for imx7d-pcie and imx8mq-pcie:
> Â- power-domains: Must be set to a phandle pointing to PCIE_PHY power domain
> Â- resets: Must contain phandles to PCIe-related reset lines exposed by SRC
> ÂÂÂIP block
> @@ -52,6 +53,9 @@ Additional required properties for imx7d-pcie:
> > Â ÂÂÂÂÂÂÂ- "apps"
> > Â ÂÂÂÂÂÂÂ- "turnoff"
> Â
> +Additional required properties for imx8mq-pcie:
> +- fsl,controller-id: Logical ID of a given PCIE controller. PCIE1 is 0, PCIE2 is 1;
> +
> ÂExample:
> Â
> > Â pcie@01000000 {
> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> index 91b0194240a5..2b139acccf32 100644
> --- a/drivers/pci/controller/dwc/Kconfig
> +++ b/drivers/pci/controller/dwc/Kconfig
> @@ -90,7 +90,7 @@ config PCI_EXYNOS
> Â
> Âconfig PCI_IMX6
> > Â bool "Freescale i.MX6 PCIe controller"
> > - depends on SOC_IMX6Q || (ARM && COMPILE_TEST)
> > + depends on SOC_IMX8MQ || SOC_IMX6Q || (ARM && COMPILE_TEST)
> > Â depends on PCI_MSI_IRQ_DOMAIN
> > Â select PCIE_DW_HOST
> Â
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 3c3002861d25..326f71698ac2 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -8,6 +8,7 @@
> > Â * Author: Sean Cross <xobs@xxxxxxxxxx>
> Â */
> Â
> +#include <linux/bitfield.h>
> Â#include <linux/clk.h>
> Â#include <linux/delay.h>
> Â#include <linux/gpio.h>
> @@ -30,6 +31,11 @@
> Â
> Â#include "pcie-designware.h"
> Â
> > +#define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9)
> > +#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10)
> > +#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
> > +#define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8)
> +
> > Â#define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
> Â
> Âenum imx6_pcie_variants {
> @@ -37,6 +43,7 @@ enum imx6_pcie_variants {
> > Â IMX6SX,
> > Â IMX6QP,
> > Â IMX7D,
> > + IMX8MQ,
> Â};
> Â
> Âstruct imx6_pcie {
> @@ -48,6 +55,7 @@ struct imx6_pcie {
> > > Â struct clk *pcie_inbound_axi;
> > > Â struct clk *pcie;
> > > Â struct regmap *iomuxc_gpr;
> > > + u32 controller_id;
> > > Â struct reset_control *pciephy_reset;
> > > Â struct reset_control *apps_reset;
> > > Â struct reset_control *turnoff_reset;
> @@ -245,7 +253,8 @@ static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
> Â{
> > Â u32 tmp;
> Â
> > - if (imx6_pcie->variant == IMX7D)
> > + if (imx6_pcie->variant == IMX7D ||
> > + ÂÂÂÂimx6_pcie->variant == IMX8MQ)
> > Â return;
> Â
> > Â pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
> @@ -261,6 +270,7 @@ static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
> > Â pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
> Â}
> Â
> +#ifdef CONFIG_ARM
> Â/*ÂÂAdded for PCI abort handling */
> Âstatic int imx6q_pcie_abort_handler(unsigned long addr,
> > Â unsigned int fsr, struct pt_regs *regs)
> @@ -294,6 +304,7 @@ static int imx6q_pcie_abort_handler(unsigned long addr,
> Â
> > Â return 1;
> Â}
> +#endif
> Â
> Âstatic void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
> Â{
> @@ -301,6 +312,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
> Â
> > Â switch (imx6_pcie->variant) {
> > Â case IMX7D:
> > + case IMX8MQ: /* FALLTHROUGH */
> > Â reset_control_assert(imx6_pcie->pciephy_reset);
> > Â reset_control_assert(imx6_pcie->apps_reset);
> > Â break;
> @@ -339,6 +351,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
> Â{
> > Â struct dw_pcie *pci = imx6_pcie->pci;
> > Â struct device *dev = pci->dev;
> > + unsigned int offset;
> > Â int ret = 0;
> Â
> > Â switch (imx6_pcie->variant) {
> @@ -369,6 +382,29 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
> > Â break;
> > Â case IMX7D:
> > Â break;
> > + case IMX8MQ:
> > + switch (imx6_pcie->controller_id) {
> > + case 0:
> > + offset = IOMUXC_GPR14;
> > + break;
> > + case 1:
> > + offset = IOMUXC_GPR16;
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> +
> > + /*
> > + Â* Set the over ride low and enabled
> > + Â* make sure that REF_CLK is turned on.
> > + Â*/
> > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
> > + ÂÂÂIMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
> > + ÂÂÂ0);
> > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
> > + ÂÂÂIMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
> > + ÂÂÂIMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
> > + break;
> > Â }
> Â
> > Â return ret;
> @@ -445,6 +481,9 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
> > Â }
> Â
> > Â switch (imx6_pcie->variant) {
> > + case IMX8MQ:
> > + reset_control_deassert(imx6_pcie->pciephy_reset);
> > + break;
> > Â case IMX7D:
> > Â reset_control_deassert(imx6_pcie->pciephy_reset);
> > Â imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
> @@ -482,7 +521,34 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
> Â
> Âstatic void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
> Â{
> > + unsigned int mask, val, offset;
> +
> > + mask = IMX6Q_GPR12_DEVICE_TYPE;
> > + valÂÂ= FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT);
> +
> > Â switch (imx6_pcie->variant) {
> > + case IMX8MQ:
> > + switch (imx6_pcie->controller_id) {
> > + case 0:
> > + offset = IOMUXC_GPR14;
> > + break;
> > + case 1:
> > + offset = IOMUXC_GPR16;
> > + mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE;
> > + valÂÂ= FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
> > + ÂÂPCI_EXP_TYPE_ROOT_PORT);
> > + break;
> > + default:
> > + return;
> > + }
> > + /*
> > + Â* TODO: Currently this code assumes external
> > + Â* oscillator is being used
> > + Â*/
> > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
> > + ÂÂÂIMX8MQ_GPR_PCIE_REF_USE_PAD,
> > + ÂÂÂIMX8MQ_GPR_PCIE_REF_USE_PAD);
> > + break;
> > Â case IMX7D:
> > Â regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> > Â ÂÂÂIMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
> @@ -518,8 +584,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
> > Â break;
> > Â }
> Â
> > - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> > - IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
> > + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val);
> Â}
> Â
> Âstatic int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
> @@ -528,7 +593,8 @@ static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
> > Â int mult, div;
> > Â u32 val;
> Â
> > - if (imx6_pcie->variant == IMX7D)
> > + if (imx6_pcie->variant == IMX7D ||
> > + ÂÂÂÂimx6_pcie->variant == IMX8MQ)
> > Â return 0;
> Â
> > Â switch (phy_rate) {
> @@ -616,6 +682,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
> > Â ÂÂÂIMX6Q_GPR12_PCIE_CTL_2);
> > Â break;
> > Â case IMX7D:
> > > + case IMX8MQ: /* FALLTHROUGH */
> > Â reset_control_deassert(imx6_pcie->apps_reset);
> > Â break;
> > Â }
> @@ -870,6 +937,10 @@ static int imx6_pcie_probe(struct platform_device *pdev)
> > Â imx6_pcie->variant =
> > Â (enum imx6_pcie_variants)of_device_get_match_data(dev);
> Â
> > + if (of_property_read_u32(node, "fsl,controller-id",
> > + Â&imx6_pcie->controller_id))
> > + imx6_pcie->controller_id = 0;
> +
> > Â dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > Â pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
> > Â if (IS_ERR(pci->dbi_base))
> @@ -921,7 +992,8 @@ static int imx6_pcie_probe(struct platform_device *pdev)
> > Â return PTR_ERR(imx6_pcie->pcie_inbound_axi);
> > Â }
> > Â break;
> > - case IMX7D:
> > + case IMX8MQ:
> > > + case IMX7D: /* FALLTHROUGH */
> > Â imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev,
> > Â ÂÂÂÂ"pciephy");
> > Â if (IS_ERR(imx6_pcie->pciephy_reset)) {
> @@ -1011,6 +1083,7 @@ static const struct of_device_id imx6_pcie_of_match[] = {
> > Â { .compatible = "fsl,imx6sx-pcie", .data = (void *)IMX6SX, },
> > Â { .compatible = "fsl,imx6qp-pcie", .data = (void *)IMX6QP, },
> > Â { .compatible = "fsl,imx7d-pcie",ÂÂ.data = (void *)IMX7D,ÂÂ},
> > + { .compatible = "fsl,imx8mq-pcie", .data = (void *)IMX8MQ, } ,
> > Â {},
> Â};
> Â
> @@ -1027,6 +1100,7 @@ static struct platform_driver imx6_pcie_driver = {
> Â
> Âstatic int __init imx6_pcie_init(void)
> Â{
> +#ifdef CONFIG_ARM
> > Â /*
> > Â Â* Since probe() can be deferred we need to make sure that
> > Â Â* hook_fault_code is not called after __init memory is freed
> @@ -1036,6 +1110,7 @@ static int __init imx6_pcie_init(void)
> > Â Â*/
> > Â hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0,
> > Â "external abort on non-linefetch");
> +#endif
> Â
> > Â return platform_driver_register(&imx6_pcie_driver);
> Â}

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