Re: [PATCH 5/5] nds32: Add document for NDS32 PMU.

From: Mark Rutland
Date: Mon Oct 22 2018 - 09:17:16 EST


On Mon, Oct 22, 2018 at 06:23:08PM +0800, Nick Hu wrote:
> Hi Mark,
>
> On Thu, Oct 18, 2018 at 10:31:32PM +0800, Mark Rutland wrote:
> > On Thu, Oct 18, 2018 at 04:43:17PM +0800, Nickhu wrote:
> > > The document for how to add NDS32 PMU
> > > in devicetree.
> > >
> > > Signed-off-by: Nickhu <nickhu@xxxxxxxxxxxxx>
> > > ---
> > > Documentation/devicetree/bindings/nds32/pmu.txt | 17 +++++++++++++++++
> > > 1 file changed, 17 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/nds32/pmu.txt
> > >
> > > diff --git a/Documentation/devicetree/bindings/nds32/pmu.txt b/Documentation/devicetree/bindings/nds32/pmu.txt
> > > new file mode 100644
> > > index 000000000000..02762b850e59
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/nds32/pmu.txt
> > > @@ -0,0 +1,17 @@
> > > +* NDS32 Performance Monitor Units
> > > +
> > > +NDS32 core have a PMU for counting cpu and cache events like cache misses.
> > > +The NDS32 PMU representation in the device tree should be done as under:
> > > +
> > > +Required properties:
> > > +
> > > +- compatilbe :
> > > + "andestech,atcpmu"
> >
> > Which CPUs have this PMU?
> >
> > I expected more specific strings, e.g. "andestech,n13-pmu" and/or
> > "andestech,andestech,nds32v3-pmu".
> >
> In nds32 V3, all of our CPU have PMU.
> So I will change the string to andestech,nds32v3-pmu.

That sounds good to me; thanks.

> > > +- interrupts : The interrupt number for NDS32 PMU is 13.
> > > +
> > > +Example:
> > > +pmu{
> > > + compatible = "andestech,atcpmu";
> > > + interrupts = <13>;
> > > +}
> >
> > The driver tried to find multiple interrupts. Is there only a single
> > interrupt in all cases?
> >
> There is only overflow interrupt for performance couner in nds32 V3.
> I will modified the driver and prepare another patch.

Ok.

Thanks,
Mark.