Re: [LINUX PATCH v10 2/2] mtd: rawnand: arasan: Add support for Arasan NAND Flash Controller

From: kbuild test robot
Date: Fri Aug 17 2018 - 11:30:45 EST


Hi Naga,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on mtd/nand/next]
[also build test WARNING on next-20180817]
[cannot apply to v4.18]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url: https://github.com/0day-ci/linux/commits/Naga-Sureshkumar-Relli/Add-support-for-Arasan-NAND-Flash-controller/20180817-224117
base: git://git.infradead.org/linux-mtd.git nand/next
config: sh-allmodconfig (attached as .config)
compiler: sh4-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.2.0 make.cross ARCH=sh

All warnings (new ones prefixed by >>):

In file included from include/linux/scatterlist.h:9:0,
from include/linux/dma-mapping.h:11,
from drivers/mtd//nand/raw/arasan_nand.c:12:
drivers/mtd//nand/raw/arasan_nand.c: In function 'anfc_rw_dma_op':
>> drivers/mtd//nand/raw/arasan_nand.c:362:16: warning: right shift count >= width of type [-Wshift-count-overflow]
writel((paddr >> 32), nfc->base + DMA_ADDR1_OFST);
^
arch/sh/include/asm/io.h:31:77: note: in definition of macro '__raw_writel'
#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
^
arch/sh/include/asm/io.h:46:62: note: in expansion of macro 'ioswabl'
#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c))
^~~~~~~
arch/sh/include/asm/io.h:56:32: note: in expansion of macro 'writel_relaxed'
#define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
^~~~~~~~~~~~~~
>> drivers/mtd//nand/raw/arasan_nand.c:362:2: note: in expansion of macro 'writel'
writel((paddr >> 32), nfc->base + DMA_ADDR1_OFST);
^~~~~~

vim +362 drivers/mtd//nand/raw/arasan_nand.c

330
331 static void anfc_rw_dma_op(struct mtd_info *mtd, uint8_t *buf, int len,
332 bool do_read, u32 prog)
333 {
334 dma_addr_t paddr;
335 struct nand_chip *chip = mtd_to_nand(mtd);
336 struct anfc_nand_controller *nfc = to_anfc(chip->controller);
337 struct anfc_nand_chip *achip = to_anfc_nand(chip);
338 u32 eccintr = 0, dir;
339 u32 pktsize = len, pktcount = 1;
340
341 if (((nfc->curr_cmd == NAND_CMD_READ0)) ||
342 (nfc->curr_cmd == NAND_CMD_SEQIN && !nfc->iswriteoob)) {
343 pktsize = achip->pktsize;
344 pktcount = DIV_ROUND_UP(mtd->writesize, pktsize);
345 }
346 anfc_setpktszcnt(nfc, pktsize, pktcount);
347
348 if (!achip->bch && nfc->curr_cmd == NAND_CMD_READ0)
349 eccintr = MBIT_ERROR;
350
351 if (do_read)
352 dir = DMA_FROM_DEVICE;
353 else
354 dir = DMA_TO_DEVICE;
355
356 paddr = dma_map_single(nfc->dev, buf, len, dir);
357 if (dma_mapping_error(nfc->dev, paddr)) {
358 dev_err(nfc->dev, "Read buffer mapping error");
359 return;
360 }
361 writel(paddr, nfc->base + DMA_ADDR0_OFST);
> 362 writel((paddr >> 32), nfc->base + DMA_ADDR1_OFST);
363 anfc_enable_intrs(nfc, (XFER_COMPLETE | eccintr));
364 writel(prog, nfc->base + PROG_OFST);
365 anfc_wait_for_event(nfc);
366 dma_unmap_single(nfc->dev, paddr, len, dir);
367 }
368

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