Re: [PATCH] MIPS: mscc: ocelot: add MIIM1 bus

[Paul Burton]

Hi Quentin,

On Wed, Jul 25, 2018 at 02:22:41PM +0200, Quentin Schulz wrote:
> There is an additional MIIM (MDIO) bus in this SoC so let's declare it
> in the dtsi.
> 
> This bus requires GPIO 14 and 15 pins that need to be muxed. There is no
> support for internal PHY reset on this bus on the contrary of MIIM0 so
> there is only one register address space and not two.
> 
> Signed-off-by: Quentin Schulz <quentin.schulz@xxxxxxxxxxx>
> ---
>  arch/mips/boot/dts/mscc/ocelot.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)

Thanks - applied to mips-next for 4.19.

Paul