Re: [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SDM845

[Stephen Boyd]

Quoting Manu Gautam (2018-04-18 09:38:41)
> Hi Amit,
> 
> 
> On 4/18/2018 6:33 PM, Amit Nischal wrote:
> >>> +ÂÂÂÂÂÂ /* Disable the GPLL0 active input to MMSS and GPU via MISC registersÂ*/
> >>> +ÂÂÂÂÂÂÂregmap_update_bits(regmap,Â0x09ffc,Â0x3,Â0x3);
> >>> +ÂÂÂÂÂÂÂregmap_update_bits(regmap,Â0x71028,Â0x3,Â0x3);
> >>
> >> IÂthinkÂwe'llÂhaveÂtoÂthrowÂinÂtheÂpipeÂclkÂbranchÂstuffÂinÂhereÂtoo?
> >> AndÂthenÂdropÂtheÂpipeÂclksÂfromÂtheÂdriver?
> >
> > AllÂtheÂUSBÂpipeÂclocksÂwouldÂbeÂtakenÂcare.ÂTheÂPCIEÂpipeÂbranch
> > clocksÂwouldÂhaveÂtoÂbeÂexplicitlyÂdisabledÂsoÂasÂtoÂretainÂthe
> > memoryÂlogic.ÂOtherwise,ÂitÂwouldÂleadÂtoÂmemoryÂcorruptionÂinÂcase
> > the external source is directly disabled without disabling the branch clock. 
> 
> PHY driver is same for both USB and PCIE and both PHYs use pipe_clk.
> If there is indeed some limitation and pipe_clk cant be left enabled
> always then I will suggest to not change pipe_clk handling for USB as well.
> 

Right. This is concerning if we have a half way solution.

Just to clarify my understanding, are you saying that the pcie pipe clks
are also tied to the memory logic and so toggling them on/off is used to
reset the memories inside the phy? Or the memories inside the
controller? What is the pipe clk clocking in these cases?