Re: [GIT PULL] x86/build changes for v4.17

[Peter Zijlstra]

On Thu, Apr 05, 2018 at 10:04:46AM +0200, Ingo Molnar wrote:
>    http://www.agner.org/optimize/instruction_tables.pdf
> 
> The SkyLake costs for 'BT', 'AND' and 'TEST' variants are:
> 
>                   BT             m,i               2               2         p06 p23                   0.5

>                 TEST           m,r/i               1               2       p0156 p23          1        0.5

These two I would imagine (I tend to forget about the TEST instruction).
And while they're of equal speed, TEST has more ports available if I
read that right. But yes, on SKL it doesn't matter much.

But if you go back in history (a lot) then you'll find BT being far more
expensive than TEST.

On the original Pentium for example TEST-m,r/i is 2 cycles, but BT-m,i
is 4-9 cycles.

But yes, going by the tables that's all hysterical raisins, modern cores
don't much care.