Re: [PATCH RESEND] CLK: ARC: Set initial pll output frequency specified in device tree

[Alexey Brodkin]

Hi Vladimir,

On Tue, 2017-11-14 at 19:01 +0200, Vladimir Zapolskiy wrote:
> On 11/14/2017 02:20 PM, Eugeniy Paltsev wrote:
> > 
> > Add option to set initial output frequency of plls via
> > "clock-frequency" property in pll's device tree node.
> > This frequency will be set while pll driver probed.
> > 
> > The usage example is setting CPU clock frequency on boot
> > See discussion:
> > https://urldefense.proofpoint.com/v2/url?u=https-3A__www.mail-2Darchive.com_linux-2Dsnps-2Darc-40lists.infradead.org_msg02689.html&d=DwICAg&c=DPL6
> > _X_6JkXFx7AXWqB0tg&r=lqdeeSSEes0GFDDl656eViXO7breS55ytWkhpk5R81I&m=vTFoSv1E8NyQC8nqe6pwvuTDxGvEefhAdGwAoABOrY4&s=sbmMnczdKP317bN973cZn2WcYF29kVMLW
> > chYfhSGT2M&e=
> > 
> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@xxxxxxxxxxxx>
> > ---
> > Â.../bindings/clock/snps,hsdk-pll-clock.txtÂÂÂÂÂÂÂÂÂ|ÂÂ5 ++++
> > Â.../devicetree/bindings/clock/snps,pll-clock.txtÂÂÂ|ÂÂ5 ++++
> > Âdrivers/clk/axs10x/pll_clock.cÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ| 34 ++++++++++++++++++++--
> > Âdrivers/clk/clk-hsdk-pll.cÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ| 34 ++++++++++++++++++++--
> > Â4 files changed, 74 insertions(+), 4 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt
> > index c56c755..5703059 100644
> > --- a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt
> > +++ b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt
> > @@ -13,6 +13,10 @@ Required properties:
> > Â- clocks: shall be the input parent clock phandle for the PLL.
> > Â- #clock-cells: from common clock binding; Should always be set to 0.
> > Â
> > +Optional properties:
> > +- clock-frequency: output frequency generated by pll in Hz which will be set
> > +while probing. Should be a single cell.
> > +
> > ÂExample:
> > Â	input_clk: input-clk {
> > Â		clock-frequency = <33333333>;
> > @@ -25,4 +29,5 @@ Example:
> > Â		reg = <0x00 0x10>;
> > Â		#clock-cells = <0>;
> > Â		clocks = <&input_clk>;
> > +		clock-frequency = <1000000000>;
> > Â	};
> > diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt
> > index 11fe487..5908f99 100644
> > --- a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt
> > +++ b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt
> > @@ -13,6 +13,10 @@ registers and second for corresponding LOCK CGU register.
> > Â- clocks: shall be the input parent clock phandle for the PLL.
> > Â- #clock-cells: from common clock binding; Should always be set to 0.
> > Â
> > +Optional properties:
> > +- clock-frequency: output frequency generated by pll in Hz which will be set
> > +while probing. Should be a single cell.
> > +
> > ÂExample:
> > Â	input-clk: input-clk {
> > Â		clock-frequency = <33333333>;
> > @@ -25,4 +29,5 @@ Example:
> > Â		reg = <0x80 0x10>, <0x100 0x10>;
> > Â		#clock-cells = <0>;
> > Â		clocks = <&input-clk>;
> > +		clock-frequency = <100000000>;
> > Â	};
> 
> You may check Documentation/devicetree/bindings/clock/clock-bindings.txt
> about how to assign initial clock rates, in general 'clock-frequency'
> property is a property of clock consumers with two exceptions of simple
> clock sources, namely it is used in fixed clock and PWM clock bindings.

I think that's what we agreed on with Rob Herring back in the day.
Have you checked this post of him on the topic?
http://lists.infradead.org/pipermail/linux-snps-arc/2017-September/002909.html

Just FYI it all started from my question here:
http://lists.infradead.org/pipermail/linux-snps-arc/2017-September/002900.html

-Alexey