[PATCH v2 0/8] MT2712 IOMMU SUPPORT

[Yong Wu]

This patchset mainly adds support for M4U of mt2712.

The M4U in mt2712 is MTK's generation2 M4U which use the ARM
Short-descriptor like mt8173. The main difference is that there are 2
M4Us and 2 smi-commons in mt2712, while there is only 1 M4U and 1
smi-common in mt8173. The purpose is for balance the bandwidth.

The mt2712 M4U-SMI HW diagram is as below:

                            EMI
                             |
              ------------------------------------
              |                                  |
             M4U0                              M4U1
              |                                  |
         smi-common0                        smi-common1
              |                                  |
  -------------------------       --------------------------------
  |     |     |     |     |       |         |        |     |     |
  |     |     |     |     |       |         |        |     |     |
larb0 larb1 larb2 larb3 larb6    larb4    larb5    larb7 larb8 larb9
disp0 vdec  cam   venc   jpg  mdp1/disp1 mdp2/disp2 mdp3 vdo/nr tvd

This patchset is based on v4.13-rc1, Also it base on Robin's[1],
Honghui[2],Arvind[3], all have been applied. Currently it don't contain
the dtsi part.

The patch 1 adds the binding for MT2712 IOMMU, the patch 2 is a
prepared patch for mt2712, the patch 3 adds the MT2712 IOMMU support.
the patch 4/5 improve the m4u flow for mt2712,
the last patch 6/7/8 mainly fix bug or improve code.

[1]:https://patchwork.kernel.org/patch/9828671/
[2]:https://patchwork.kernel.org/patch/9880223/
[3]:https://patchwork.kernel.org/patch/9892759/

change log:
v2:
 1) Add larb8 and larb9 in the HW diagram. larb8 and larb9 are called
    by the bdpsys larb, they are a little special, their mmu_en register
    offset is different from the normal larb. Fortunately, their mmu_en
    register is enabled defaultly, we don't need set again.
    After adding larb8 and larb9, the larb number is over 8, therefore,
    MTK_LARB_NR_MAX also is increased.
 2) Add a prepared patch that moving the MTK_M4U_TO_LARB/PORT into the
    c file.
 3) Discard the original patch[7/8] which was only a cleanup for SMI,
    It's unnecessary for this patch-set.
 4) Use subsys_initcall instead of IOMMU_OF_DECLARE according to
    Robin's suggestion. Also, Improve some coding format, like using
    for_each_set_bit and changing the definition of
    F_MMU_TF_PROTECT_SEL.

v1:
https://lists.linuxfoundation.org/pipermail/iommu/2017-August/023664.html

Yong Wu (8):
  dt-bindings: mediatek: Add binding for mt2712 IOMMU and SMI
  iommu/mediatek: Move MTK_M4U_TO_LARB/PORT into mtk_iommu.c
  iommu/mediatek: Add mt2712 IOMMU support
  iommu/mediatek: Merge 2 M4U HWs into one iommu domain
  iommu/mediatek: Move pgtable allocation into domain_alloc
  iommu/mediatek: Disable iommu clock when system suspend
  iommu/mediatek: Enlarge the validate PA range for 4GB mode
  memory: mtk-smi: Degrade SMI init to module_init

 .../devicetree/bindings/iommu/mediatek,iommu.txt   |   6 +-
 .../memory-controllers/mediatek,smi-common.txt     |   6 +-
 .../memory-controllers/mediatek,smi-larb.txt       |   5 +-
 drivers/iommu/mtk_iommu.c                          | 214 +++++++++++++--------
 drivers/iommu/mtk_iommu.h                          |   9 +
 drivers/memory/mtk-smi.c                           |  65 ++++++-
 include/dt-bindings/memory/mt2712-larb-port.h      | 102 ++++++++++
 include/dt-bindings/memory/mt8173-larb-port.h      |   4 -
 include/soc/mediatek/smi.h                         |   2 +-
 9 files changed, 314 insertions(+), 99 deletions(-)
 create mode 100644 include/dt-bindings/memory/mt2712-larb-port.h

-- 
1.9.1