*> From:* Vineet Gupta <Vineet.Gupta1@xxxxxxxxxxxx>
*> Sent:* Thursday, June 8, 2017 7:38 PM
>>
>> With simulator we just turn this configuration on, so we redirect the Legacy
>> Synopsys L2 ISR from nSIM into machine check.
>> This way we end up just like with silicon ð
>This doesn't make sense :-)
>In simulation (where L2 interrupt is asserted), you need to handle it as such -
>say reading out the banked regs for L2 interrupt. What you are doing here is
>handling it like an exception which won't work . I really don't see the point of
>this "alignment" - hardware and simulation are different. simulation semantics are
>already supported by generic ARC code. And for silicon case, the existing vector
>woudl MachineCheck would work for both K and U. So I'm not sure what we are trying
>to achieve here !
With EZsim we try to simulate NPS400 CTOP core and not ARC core, and as such we strive to have similar echo system for both silicon and its simulator.
If we could, we would alter nSIM to behave just like our silicon.
So in current situation where we lack doing so we suffice in single pretty small adjustment in OS (platform specific code).