Re: [PATCH 4/4] staging: rtl8723bs: checkpatch - resolve indentation and line width

[Greg KH]

On Thu, May 11, 2017 at 06:45:24PM -0700, Matthew Giassa wrote:
> +#define	REG_INT_MIG_8723B		0x0304	/* Interrupt Migration */
> +#define	REG_BCNQ_DESA_8723B		0x0308	/* TX Beacon Descriptor Address
> +						 */
> +#define	REG_HQ_DESA_8723B		0x0310	/* TX High Queue Descriptor
> +						 * Address
> +						 */

Ick, that looks worse to me now, doesn't it to you?  Please leave the
original as-is.

Also, always test-build your patches :)

thanks,

greg k-h