Re: [PATCH v2] stmmac: CSR clock configuration fix

[Phil Reid]

G'day Joao,
On 23/12/2016 01:06, Joao Pinto wrote:
> Às 4:57 PM de 12/22/2016, Phil Reid escreveu:
> > On 22/12/2016 23:47, Joao Pinto wrote:
> > > Hello Phil,
> > >
> > > Às 3:42 PM de 12/22/2016, Phil Reid escreveu:
> > > > G'day Joao,
> > > >
> > > > On 22/12/2016 20:38, Joao Pinto wrote:
> > > > > When testing stmmac with my QoS reference design I checked a problem in the
> > > > > CSR clock configuration that was impossibilitating the phy discovery, since
> > > > > every read operation returned 0x0000ffff. This patch fixes the issue.
> > > > >
> > > > > Signed-off-by: Joao Pinto <jpinto@xxxxxxxxxxxx>
> > > > > ---
> > > > > changes v1->v2 (David Miller)
> > > > > - DWMAC100 and DWMAC1000 csr clocks masks should also be fixed for the patch
> > > > > to make sense
> > > > >
> > > > >  drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c | 2 +-
> > > > >  drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c  | 2 +-
> > > > >  drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c    | 8 ++++----
> > > > >  3 files changed, 6 insertions(+), 6 deletions(-)
> > > > >
> > > > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
> > > > > b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
> > > > > index b21d03f..94223c8 100644
> > > > > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
> > > > > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
> > > > > @@ -539,7 +539,7 @@ struct mac_device_info *dwmac1000_setup(void __iomem
> > > > > *ioaddr, int mcbins,
> > > > >      mac->mii.reg_shift = 6;
> > > > >      mac->mii.reg_mask = 0x000007C0;
> > > > >      mac->mii.clk_csr_shift = 2;
> > > > > -    mac->mii.clk_csr_mask = 0xF;
> > > > > +    mac->mii.clk_csr_mask = GENMASK(4, 2);
> > > >
> > > > Should this not be GENMASK(5,2)
> > >
> > > According to Universal MAC databook (valid for MAC100 and MAC1000), we have:
> > >
> > > Bits: 4:2
> > > 000 60-100 MHz clk_csr_i/42
> > > 001 100-150 MHz clk_csr_i/62
> > > 010 20-35 MHz clk_csr_i/16
> > > 011 35-60 MHz clk_csr_i/26
> > > 100 150-250 MHz clk_csr_i/102
> > > 101 250-300 MHz clk_csr_i/124
> > > 110, 111 Reserved
> > >
> > > So only bits 2, 3 and 4 should be masked.
> > >
> > > Thanks.
> > But this is a change in behaviour from what was there isn't.
> > Previous mask was 4 bits. now it's 3.
> >
> > And for example the altera socfgpa implementation in the cyclone V has valid values
> > for values 0x8-0xf, using bit 5:2.
>
> According to the databook, bit 5 is reserved and RO. When reserved, it is
> possible to customize. Is that the case? If there is hardware using the 5th bit
> we can put it GENMASK(5, 2) with no problem.
I've also checked the Aria 10 documentation and bit 5 is also RW.
The following options are documented and supported
    1000: CSR clock/4
    1001: CSR clock/6
    1010: CSR clock/8
    1011: CSR clock/10
    1100: CSR clock/12
    1101: CSR clock/14
    1110: CSR clock/16
    1111: CSR clock/18
They do mention that these values will probably be outside the IEEE 802.3 specified range.

But there's at least a couple of cores out there where GENMASK(5,2) is valid.
Can't say if anyone is using that setting thou.


--
Regards
Phil Reid