Re: [PATCH v6: 1/4] x86/msr: Add R3MWAIT register and bit to msr-info.h

[Thomas Gleixner]

On Thu, 27 Oct 2016, Grzegorz Andrejczuk wrote:
> Intel Xeon Phi x200 (codenamed Knights Landing) has MSR
> MISC_THD_FEATURE_ENABLE 0x140.

Oh well. I just reviewed another patch which names this register:

   MSR_MISC_FEATURE_ENABLES

and that's how it's named in this document:

http://www.intel.com/content/dam/www/public/us/en/documents/application-notes/virtualization-technology-flexmigration-application-note.pdf
 
Can Intel please get its act together and document that register proper in
the SDM?

Thanks,

	tglx