Re: [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier

[Matt Redfearn]

On 31/08/16 12:48, Peter Zijlstra wrote:
> On Wed, Aug 31, 2016 at 11:44:35AM +0100, Matt Redfearn wrote:
> > Since R2 of the MIPS architecture, SYNC(0x10) has been an optional but
> > architecturally defined ordering barrier. If a CPU does not implement it,
> > the arch specifies that it must fall back to SYNC(0).
> >
> > Define the barrier type and always use it in the pm-cps code rather than
> > falling back to the heavyweight sync(0) such that we can benefit from
> > the lighter weight sync.
> Changelog does not explain what 0x10 is, nor why its sufficient for this
> case.

Hi Peter,

The code previously had 0x10 as a magic number, this patch just replaces 
that with a #defined name. The value is documented in the MIPS64 
instruction set manual, https://imgtec.com/?do-download=4302, table 6.5.

This sync type has been standard since MIPSr2. That document also states 
that "If an implementation does not use one of these non-zero values to 
define a different synchronization behavior, then that non-zero value of 
stype must act the same as stype zero completion barrier." As such, 
stype_ordering can always be set to this sync type rather than setting 
it only for certain CPUs.

Thanks,
Matt

> Changelog also fails to explain why you do this.
> How do you expect anybody to review this?