[Patch v4 5/9] driver/edac/fsl_ddr: Add DDR types

[York Sun]

The compatible DDR controllers may support DDR, DDR2, DDR3, DDR4. An
individual controller doesn't support all of them. EDAC driver reads
the controller to determine which mode is running.

Signed-off-by: York Sun <york.sun@xxxxxxx>

---
Change log
  v4: Drop DSC_SDTYPE_DDR* macros, use naked numbers as suggested
      Update commit message.
  v3: no change
  v2: no change

 drivers/edac/fsl_ddr_edac.c | 24 ++++++++++++++++--------
 drivers/edac/fsl_ddr_edac.h |  4 ----
 2 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c
index 2675833..46b00e1 100644
--- a/drivers/edac/fsl_ddr_edac.c
+++ b/drivers/edac/fsl_ddr_edac.c
@@ -371,30 +371,36 @@ static void fsl_ddr_init_csrows(struct mem_ctl_info *mci)
 	sdtype = sdram_ctl & DSC_SDTYPE_MASK;
 	if (sdram_ctl & DSC_RD_EN) {
 		switch (sdtype) {
-		case DSC_SDTYPE_DDR:
+		case 0x02000000:
 			mtype = MEM_RDDR;
 			break;
-		case DSC_SDTYPE_DDR2:
+		case 0x03000000:
 			mtype = MEM_RDDR2;
 			break;
-		case DSC_SDTYPE_DDR3:
+		case 0x07000000:
 			mtype = MEM_RDDR3;
 			break;
+		case 0x05000000:
+			mtype = MEM_RDDR4;
+			break;
 		default:
 			mtype = MEM_UNKNOWN;
 			break;
 		}
 	} else {
 		switch (sdtype) {
-		case DSC_SDTYPE_DDR:
+		case 0x02000000:
 			mtype = MEM_DDR;
 			break;
-		case DSC_SDTYPE_DDR2:
+		case 0x03000000:
 			mtype = MEM_DDR2;
 			break;
-		case DSC_SDTYPE_DDR3:
+		case 0x07000000:
 			mtype = MEM_DDR3;
 			break;
+		case 0x05000000:
+			mtype = MEM_DDR4;
+			break;
 		default:
 			mtype = MEM_UNKNOWN;
 			break;
@@ -499,8 +505,10 @@ int fsl_mc_err_probe(struct platform_device *op)
 	}
 
 	edac_dbg(3, "init mci\n");
-	mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 |
-	    MEM_FLAG_DDR | MEM_FLAG_DDR2;
+	mci->mtype_cap = MEM_FLAG_DDR | MEM_FLAG_RDDR |
+			 MEM_FLAG_DDR2 | MEM_FLAG_RDDR2 |
+			 MEM_FLAG_DDR3 | MEM_FLAG_RDDR3 |
+			 MEM_FLAG_DDR4 | MEM_FLAG_RDDR4;
 	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
 	mci->edac_cap = EDAC_FLAG_SECDED;
 	mci->mod_name = EDAC_MOD_STR;
diff --git a/drivers/edac/fsl_ddr_edac.h b/drivers/edac/fsl_ddr_edac.h
index 1eccc62..4ccee29 100644
--- a/drivers/edac/fsl_ddr_edac.h
+++ b/drivers/edac/fsl_ddr_edac.h
@@ -50,10 +50,6 @@
 #define DSC_DBW_64	0x00000000
 
 #define DSC_SDTYPE_MASK		0x07000000
-
-#define DSC_SDTYPE_DDR		0x02000000
-#define DSC_SDTYPE_DDR2		0x03000000
-#define DSC_SDTYPE_DDR3		0x07000000
 #define DSC_X32_EN	0x00000020
 
 /* Err_Int_En */
-- 
2.7.4