Re: [PATCH v2 16/17] sh: I/O DATA HDL-U (a.k.a. landisk) Device Tree

From: Yoshinori Sato
Date: Mon Jun 13 2016 - 10:23:52 EST


On Mon, 13 Jun 2016 17:13:37 +0900,
Geert Uytterhoeven wrote:
>
> Hi Sato-san,
>
> On Sun, Jun 12, 2016 at 8:54 AM, Yoshinori Sato
> <ysato@xxxxxxxxxxxxxxxxxxxx> wrote:
> > --- /dev/null
> > +++ b/arch/sh/boot/dts/landisk.dts
> > @@ -0,0 +1,150 @@
>
> > + pllclk: pllclk {
> > + compatible = "renesas,sh7750-pll-clock";
> > + clocks = <&oclk>;
> > + #clock-cells = <0>;
> > + renesas,mult = <12>;
> > + reg = <0xffc00000 2>, <0xffc00008 4>;
> > + };
> > + iclk: iclk {
> > + compatible = "renesas,sh7750-div-clock";
> > + clocks = <&pllclk>;
> > + #clock-cells = <0>;
> > + reg = <0xffc00000 2>;
> > + renesas,offset = <6>;
> > + clock-output-names = "ick";
>
> clock-output-names is deprecated for clocks providing a single output.
>
> > + };
> > + bclk: bclk {
> > + compatible = "renesas,sh7750-div-clock";
> > + clocks = <&pllclk>;
> > + #clock-cells = <0>;
> > + reg = <0xffc00000 2>;
> > + renesas,offset = <3>;
> > + clock-output-names = "bck";
> > + };
> > + fclk: fclk {
> > + compatible = "renesas,sh7750-div-clock";
> > + clocks = <&pllclk>;
> > + #clock-cells = <0>;
> > + reg = <0xffc00000 2>;
> > + renesas,offset = <0>;
> > + clock-output-names = "fck";
> > + };
>
> I think it will be much easier for maintenance and code reuse to just have a
> single "cpg" node that's compatible with "renesas,sh7750-cpg", covering all
> CPG registers. Especially since the various clocks use the same registers.
>
> Cfr. drivers/clk/renesas/cpg-mssr.c.

OK.
I'll try.

> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds

--
Yoshinori Sato
<ysato@xxxxxxxxxxxxxxxxxxxx>