Re: [PATCH v2 1/2] Documentation: bindings: add dt doc for Rockchip PCIe controller

From: Shawn Lin
Date: Sat Jun 11 2016 - 21:35:18 EST


å 2016/6/10 12:01, Doug Anderson åé:
Shawn,

On Wed, Jun 8, 2016 at 1:05 AM, Shawn Lin <shawn.lin@xxxxxxxxxxxxxx> wrote:
+pcie0: pcie@f8000000 {
+ compatible = "rockchip,rk3399-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
+ <&cru PCLK_PCIE>;
+ clock-names = "aclk", "aclk-perf",
+ "hclk";

Code also requires a "pm" clock.

+ bus-range = <0x0 0x1>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names: "sys", "legacy", "client";

Shouldn't be ":", should be "=".


+ assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
+ assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
+ assigned-clock-rates = <100000000>;
+ ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+ ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
+ 0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;

nit: I don't thin it's common to have spaces before/after the ">" and "<".
nit: Be consistent about 0 vs. 0x0 in ranges.


+ num-lanes = <4>;
+ reg = < 0x0 0xf8000000 0x0 0x2000000 >, < 0x0 0xfd000000 0x0 0x1000000 >;
+ reg-name = "axi-base", "apb-base";

Should be "reg-names" (with an "s")


+ resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
+ <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
+ reset-names = "core", "mgmt", "mgmt-sticky", "pipe";

You have 5 resets but 4 reset names. That doesn't seem right. Code
shows you only getting 4, so presumably you need to remove the
SRST_PCIEPHY one.

Thanks for catching these above as I forgot to rework the this sample.



-Doug

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--
Best Regards
Shawn Lin