[PATCH] sb_edac: Enable channel interleave hashing support for HSX/BDX

From: patrickg
Date: Tue Mar 29 2016 - 17:41:40 EST


Patch implements channel interleave hash if MCChanHashEn is set in HA on Haswell/Broadwell. If this bit was set, but no math was used to calculate the correct interleave index, sb_edac would place errors on incorrect channels.

diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
index 93f0d41..02f6fd6 100644
--- a/drivers/edac/sb_edac.c
+++ b/drivers/edac/sb_edac.c
@@ -361,7 +361,7 @@ struct sbridge_pvt {
struct sbridge_channel channel[NUM_CHANNELS];

/* Memory type detection */
- bool is_mirrored, is_lockstep, is_close_pg;
+ bool is_mirrored, is_lockstep, is_close_pg, is_ch_hash;

/* Fifo double buffers */
struct mce mce_entry[MCE_LOG_LEN];
@@ -1060,6 +1060,16 @@ static inline u8 sad_pkg_ha(u8 pkg)
return (pkg >> 2) & 0x1;
}

+/* Hash bits 12 through 27 against the two interleave bits */
+static u32 haswell_chan_hash(u32 interleave, u64 addr) {
+ u8 i=0, bits=0;
+ for (i=12; i<28; i+=2) {
+ bits = (addr >> i) & 0x3;
+ interleave ^= bits;
+ }
+ return interleave;
+}
+
/****************************************************************************
Memory check routines
****************************************************************************/
@@ -1616,6 +1626,13 @@ static int get_dimm_config(struct mem_ctl_info *mci)
KNL_MAX_CHANNELS : NUM_CHANNELS;
u64 knl_mc_sizes[KNL_MAX_CHANNELS];

+ /* On HSX/BDX, check channel hash bit. */
+ pvt->is_ch_hash = 0;
+ if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
+ pci_read_config_dword(pvt->pci_ha0, HASWELL_HASYSDEFEATURE2, &reg);
+ pvt->is_ch_hash = GET_BITFIELD(reg, 21, 21);
+ }
+
if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL ||
pvt->info.type == KNIGHTS_LANDING)
pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, &reg);
@@ -2120,10 +2137,13 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
ch_way = TAD_CH(reg) + 1;
sck_way = 1 << TAD_SOCK(reg);

- if (ch_way == 3)
+ if (ch_way == 3) {
idx = addr >> 6;
- else
+ } else {
idx = (addr >> (6 + sck_way + shiftup)) & 0x3;
+ if (pvt->is_ch_hash)
+ idx = haswell_chan_hash(idx, addr);
+ }
idx = idx % ch_way;

/*