Re: smp_read_barrier_depends() for Blackfin

From: Paul E. McKenney
Date: Sun Jan 03 2016 - 13:08:34 EST


On Sun, Jan 03, 2016 at 06:25:39PM +0200, Petko Manolov wrote:
> Content preview: Hi Paul, Ingo, It seems to me that smp_read_barrier_depends
> (which resolves to ___raw_smp_check_barrier_asm) is overdoing it, unless
> that particular part it is written for is a disaster in terms of cache coherency.
> [...]
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> Hi Paul, Ingo,
>
> It seems to me that smp_read_barrier_depends (which resolves to
> ___raw_smp_check_barrier_asm) is overdoing it, unless that particular part it is
> written for is a disaster in terms of cache coherency.
>
> So far this is the only architecture that i know of (baring Alpha) which employs
> non-empty read_barrier_depends(). I am wondering if this is really needed or
> those who did the arch port got overly enthusiastic. If it is the former then
> you may include another example of crazy architecture in your book. :)

Hello, Petko,

I must defer to the architecture maintainers. That said, there was a time
when the blackfin maintainer were trying to make an SMP system without
cache coherence, that is, by simply wiring two UP-only blackfin CPUs
into a single system. They were using cache-flush tricks to make things
more-or-less work. And their ___raw_smp_check_barrier_asm() does look
to be flushing caches, so maybe that is what is happening here. And the
comment header for read_barrier_depends() seems to support this view.

Adding the blackfin folks and the usual lists on CC. Might get
us something better than my half-remembered hearsay and possible
misinterpretations of header comments. ;-)

That said, cache-incoherent systems might well be a good addition to
the book.

Thanx, Paul

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