Re: [PATCH v3 2/4] drivers: clk: st: PLL rate change implementation for DVFS

[Stephen Boyd]

On 10/05, Gabriel Fernandez wrote:
> @@ -452,7 +651,7 @@ static const struct clk_ops st_pll1200c32_ops = {
>  static struct clk * __init clkgen_pll_register(const char *parent_name,
>  				struct clkgen_pll_data	*pll_data,
>  				void __iomem *reg,
> -				const char *clk_name)
> +				const char *clk_name, spinlock_t *lock)

Is there a reason we pass lock here but never use it in this
function?

>  {
>  	struct clkgen_pll *pll;
>  	struct clk *clk;

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