[PATCH] MIPS: bugfix of local_r4k_flush_icache_range - added L2 flush

[Leonid Yegoshin]

This function is used to flush code used in NMI and EJTAG debug exceptions.
However, during that exceptions the Status.ERL bit is set, which means
that code runs as UNCACHABLE. So, flush code down to memory is needed.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@xxxxxxxxxx>
---
 arch/mips/mm/c-r4k.c |   10 +---------
 1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 0dbb65a51ce5..9f0299bb9a2a 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -666,17 +666,9 @@ static inline void local_r4k_flush_icache_range(unsigned long start, unsigned lo
 			break;
 		}
 	}
-#ifdef CONFIG_EVA
-	/*
-	 * Due to all possible segment mappings, there might cache aliases
-	 * caused by the bootloader being in non-EVA mode, and the CPU switching
-	 * to EVA during early kernel init. It's best to flush the scache
-	 * to avoid having secondary cores fetching stale data and lead to
-	 * kernel crashes.
-	 */
+
 	bc_wback_inv(start, (end - start));
 	__sync();
-#endif
 }
 
 static inline void local_r4k_flush_icache_range_ipi(void *args)

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