[PATCH v3 1/3] clk: qcom: Fix clk_get_parent function return value

From: Georgi Djakov
Date: Fri Mar 20 2015 - 12:30:41 EST


According to the common clock framework API, the clk_get_parent() function
should return u8. Currently we are returning negative values on error. Fix
this and use the default parent in case of an error.

Signed-off-by: Georgi Djakov <georgi.djakov@xxxxxxxxxx>
---
drivers/clk/qcom/clk-rcg.c | 26 +++++++++++++++++++-------
drivers/clk/qcom/clk-rcg2.c | 7 +++++--
2 files changed, 24 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c
index 466f30ca65c2..59a093e56366 100644
--- a/drivers/clk/qcom/clk-rcg.c
+++ b/drivers/clk/qcom/clk-rcg.c
@@ -47,15 +47,20 @@ static u8 clk_rcg_get_parent(struct clk_hw *hw)
struct clk_rcg *rcg = to_clk_rcg(hw);
int num_parents = __clk_get_num_parents(hw->clk);
u32 ns;
- int i;
+ int i, ret;

- regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
+ ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
+ if (ret)
+ goto err;
ns = ns_to_src(&rcg->s, ns);
for (i = 0; i < num_parents; i++)
if (ns == rcg->s.parent_map[i])
return i;

- return -EINVAL;
+err:
+ pr_debug("%s: Clock %s has invalid parent, using default.\n",
+ __func__, __clk_get_name(hw->clk));
+ return 0;
}

static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank)
@@ -70,21 +75,28 @@ static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw)
int num_parents = __clk_get_num_parents(hw->clk);
u32 ns, reg;
int bank;
- int i;
+ int i, ret;
struct src_sel *s;

- regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
+ ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
+ if (ret)
+ goto err;
bank = reg_to_bank(rcg, reg);
s = &rcg->s[bank];

- regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
+ ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
+ if (ret)
+ goto err;
ns = ns_to_src(s, ns);

for (i = 0; i < num_parents; i++)
if (ns == s->parent_map[i])
return i;

- return -EINVAL;
+err:
+ pr_debug("%s: Clock %s has invalid parent, using default.\n",
+ __func__, __clk_get_name(hw->clk));
+ return 0;
}

static int clk_rcg_set_parent(struct clk_hw *hw, u8 index)
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 742acfa18d63..6f27c5c614cc 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -69,7 +69,7 @@ static u8 clk_rcg2_get_parent(struct clk_hw *hw)

ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
if (ret)
- return ret;
+ goto err;

cfg &= CFG_SRC_SEL_MASK;
cfg >>= CFG_SRC_SEL_SHIFT;
@@ -78,7 +78,10 @@ static u8 clk_rcg2_get_parent(struct clk_hw *hw)
if (cfg == rcg->parent_map[i])
return i;

- return -EINVAL;
+err:
+ pr_debug("%s: Clock %s has invalid parent, using default.\n",
+ __func__, __clk_get_name(hw->clk));
+ return 0;
}

static int update_config(struct clk_rcg2 *rcg)
--
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