[PATCH] rnndb: Update DSI core and PHY registers for 8084

From: Hai Li
Date: Fri Mar 13 2015 - 19:22:07 EST

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DSI core registers in DSI6G are compatible with the old versions.
The offsets are 4-byte shift down because of the addition of a
HW_VERSION register. This difference will be handled in source code.

DSI PHY registers are incompatible. This change adds a new domain
for 28nm PHY and PHY regulator, which are used in 8084 and some other
chips.

Signed-off-by: Hai Li <hali@xxxxxxxxxxxxxx>
---
rnndb/dsi/dsi.xml | 212 ++++++++++++++++++++++++++++++++++++++++++++++++------
1 file changed, 191 insertions(+), 21 deletions(-)

diff --git a/rnndb/dsi/dsi.xml b/rnndb/dsi/dsi.xml
index 19898e1..480ec46 100644
--- a/rnndb/dsi/dsi.xml
+++ b/rnndb/dsi/dsi.xml
@@ -10,11 +10,11 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<value name="NON_BURST_SYNCH_EVENT" value="1"/>
<value name="BURST_MODE" value="2"/>
</enum>
- <enum name="dsi_dst_format">
- <value name="DST_FORMAT_RGB565" value="0"/>
- <value name="DST_FORMAT_RGB666" value="1"/>
- <value name="DST_FORMAT_RGB666_LOOSE" value="2"/>
- <value name="DST_FORMAT_RGB888" value="3"/>
+ <enum name="dsi_vid_dst_format">
+ <value name="VID_DST_FORMAT_RGB565" value="0"/>
+ <value name="VID_DST_FORMAT_RGB666" value="1"/>
+ <value name="VID_DST_FORMAT_RGB666_LOOSE" value="2"/>
+ <value name="VID_DST_FORMAT_RGB888" value="3"/>
</enum>
<enum name="dsi_rgb_swap">
<value name="SWAP_RGB" value="0"/>
@@ -26,11 +26,30 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
</enum>
<enum name="dsi_cmd_trigger">
<value name="TRIGGER_NONE" value="0"/>
+ <value name="TRIGGER_SEOF" value="1"/>
<value name="TRIGGER_TE" value="2"/>
<value name="TRIGGER_SW" value="4"/>
<value name="TRIGGER_SW_SEOF" value="5"/>
<value name="TRIGGER_SW_TE" value="6"/>
</enum>
+ <enum name="dsi_cmd_dst_format">
+ <value name="CMD_DST_FORMAT_RGB111" value="0"/>
+ <value name="CMD_DST_FORMAT_RGB332" value="3"/>
+ <value name="CMD_DST_FORMAT_RGB444" value="4"/>
+ <value name="CMD_DST_FORMAT_RGB565" value="6"/>
+ <value name="CMD_DST_FORMAT_RGB666" value="7"/>
+ <value name="CMD_DST_FORMAT_RGB888" value="8"/>
+ </enum>
+ <enum name="dsi_lane_swap">
+ <value name="LANE_SWAP_0123" value="0"/>
+ <value name="LANE_SWAP_3012" value="1"/>
+ <value name="LANE_SWAP_2301" value="2"/>
+ <value name="LANE_SWAP_1230" value="3"/>
+ <value name="LANE_SWAP_0321" value="4"/>
+ <value name="LANE_SWAP_1032" value="5"/>
+ <value name="LANE_SWAP_2103" value="6"/>
+ <value name="LANE_SWAP_3210" value="7"/>
+ </enum>
<bitset name="DSI_IRQ">
<bitfield name="CMD_DMA_DONE" pos="0" type="boolean"/>
<bitfield name="MASK_CMD_DMA_DONE" pos="1" type="boolean"/>
@@ -38,10 +57,18 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<bitfield name="MASK_CMD_MDP_DONE" pos="9" type="boolean"/>
<bitfield name="VIDEO_DONE" pos="16" type="boolean"/>
<bitfield name="MASK_VIDEO_DONE" pos="17" type="boolean"/>
+ <bitfield name="BTA_DONE" pos="20" type="boolean"/>
+ <bitfield name="MASK_BTA_DONE" pos="21" type="boolean"/>
<bitfield name="ERROR" pos="24" type="boolean"/>
<bitfield name="MASK_ERROR" pos="25" type="boolean"/>
</bitset>

+ <reg32 offset="0x00000" name="6G_HW_VERSION">
+ <bitfield name="MAJOR" low="28" high="31" type="uint"/>
+ <bitfield name="MINOR" low="16" high="27" type="uint"/>
+ <bitfield name="STEP" low="0" high="15" type="uint"/>
+ </reg32>
+
<reg32 offset="0x00000" name="CTRL">
<bitfield name="ENABLE" pos="0" type="boolean"/>
<bitfield name="VID_MODE_EN" pos="1" type="boolean"/>
@@ -56,15 +83,20 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
</reg32>

<reg32 offset="0x00004" name="STATUS0">
+ <bitfield name="CMD_MODE_ENGINE_BUSY" pos="0" type="boolean"/>
<bitfield name="CMD_MODE_DMA_BUSY" pos="1" type="boolean"/>
+ <bitfield name="CMD_MODE_MDP_BUSY" pos="2" type="boolean"/>
<bitfield name="VIDEO_MODE_ENGINE_BUSY" pos="3" type="boolean"/>
<bitfield name="DSI_BUSY" pos="4" type="boolean"/> 
+ <bitfield name="INTERLEAVE_OP_CONTENTION" pos="31" type="boolean"/>
</reg32>

- <reg32 offset="0x00008" name="FIFO_STATUS"/>
+ <reg32 offset="0x00008" name="FIFO_STATUS">
+ <bitfield name="CMD_MDP_FIFO_UNDERFLOW" pos="7" type="boolean"/>
+ </reg32>
<reg32 offset="0x0000c" name="VID_CFG0">
<bitfield name="VIRT_CHANNEL" low="0" high="1" type="uint"/> 
- <bitfield name="DST_FORMAT" low="4" high="5" type="dsi_dst_format"/>
+ <bitfield name="DST_FORMAT" low="4" high="5" type="dsi_vid_dst_format"/>
<bitfield name="TRAFFIC_MODE" low="8" high="9" type="dsi_traffic_mode"/>
<bitfield name="BLLP_POWER_STOP" pos="12" type="boolean"/>
<bitfield name="EOF_BLLP_POWER_STOP" pos="15" type="boolean"/>
@@ -74,11 +106,10 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<bitfield name="PULSE_MODE_HSA_HE" pos="28" type="boolean"/>
</reg32>
<reg32 offset="0x0001c" name="VID_CFG1">
- <bitfield name="R_SEL" pos="4" type="boolean"/>
- <bitfield name="G_SEL" pos="8" type="boolean"/>
- <bitfield name="B_SEL" pos="12" type="boolean"/>
- <bitfield name="RGB_SWAP" low="16" high="18" type="dsi_rgb_swap"/>
- <bitfield name="INTERLEAVE_MAX" low="20" high="23" type="uint"/>
+ <bitfield name="R_SEL" pos="0" type="boolean"/>
+ <bitfield name="G_SEL" pos="4" type="boolean"/>
+ <bitfield name="B_SEL" pos="8" type="boolean"/>
+ <bitfield name="RGB_SWAP" low="12" high="14" type="dsi_rgb_swap"/>
</reg32>
<reg32 offset="0x00020" name="ACTIVE_H">
<bitfield name="START" low="0" high="11" type="uint"/>
@@ -96,27 +127,53 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<bitfield name="START" low="0" high="11" type="uint"/>
<bitfield name="END" low="16" high="27" type="uint"/>
</reg32>
- <reg32 offset="0x00034" name="ACTIVE_VSYNC">
+ <reg32 offset="0x00030" name="ACTIVE_VSYNC_HPOS">
+ <bitfield name="START" low="0" high="11" type="uint"/>
+ <bitfield name="END" low="16" high="27" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00034" name="ACTIVE_VSYNC_VPOS">
<bitfield name="START" low="0" high="11" type="uint"/>
<bitfield name="END" low="16" high="27" type="uint"/>
</reg32>

<reg32 offset="0x00038" name="CMD_DMA_CTRL">
+ <bitfield name="BROADCAST_EN" pos="31" type="boolean"/>
<bitfield name="FROM_FRAME_BUFFER" pos="28" type="boolean"/>
<bitfield name="LOW_POWER" pos="26" type="boolean"/>
</reg32>
- <reg32 offset="0x0003c" name="CMD_CFG0"/>
- <reg32 offset="0x00040" name="CMD_CFG1"/>
+ <reg32 offset="0x0003c" name="CMD_CFG0">
+ <bitfield name="DST_FORMAT" low="0" high="3" type="dsi_cmd_dst_format"/>
+ <bitfield name="R_SEL" pos="4" type="boolean"/>
+ <bitfield name="G_SEL" pos="8" type="boolean"/>
+ <bitfield name="B_SEL" pos="12" type="boolean"/>
+ <bitfield name="INTERLEAVE_MAX" low="20" high="23" type="uint"/>
+ <bitfield name="RGB_SWAP" low="16" high="18" type="dsi_rgb_swap"/>
+ </reg32>
+ <reg32 offset="0x00040" name="CMD_CFG1">
+ <bitfield name="WR_MEM_START" low="0" high="7" type="uint"/>
+ <bitfield name="WR_MEM_CONTINUE" low="8" high="15" type="uint"/>
+ <bitfield name="INSERT_DCS_COMMAND" pos="16" type="boolean"/>
+ </reg32>
<reg32 offset="0x00044" name="DMA_BASE"/>
<reg32 offset="0x00048" name="DMA_LEN"/>
+ <reg32 offset="0x00054" name="CMD_MDP_STREAM_CTRL">
+ <bitfield name="DATA_TYPE" low="0" high="5" type="uint"/>
+ <bitfield name="VIRTUAL_CHANNEL" low="8" high="9" type="uint"/>
+ <bitfield name="WORD_COUNT" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00058" name="CMD_MDP_STREAM_TOTAL">
+ <bitfield name="H_TOTAL" low="0" high="11" type="uint"/>
+ <bitfield name="V_TOTAL" low="16" high="27" type="uint"/>
+ </reg32>
<reg32 offset="0x00064" name="ACK_ERR_STATUS"/>
<array offset="0x00068" name="RDBK" length="4" stride="4">
<reg32 offset="0x0" name="DATA"/>
</array>
<reg32 offset="0x00080" name="TRIG_CTRL">
- <bitfield name="DMA_TRIGGER" low="0" high="3" type="dsi_cmd_trigger"/>
- <bitfield name="MDP_TRIGGER" low="4" high="7" type="dsi_cmd_trigger"/>
- <bitfield name="STREAM" pos="8" type="boolean"/>
+ <bitfield name="DMA_TRIGGER" low="0" high="2" type="dsi_cmd_trigger"/>
+ <bitfield name="MDP_TRIGGER" low="4" high="6" type="dsi_cmd_trigger"/>
+ <bitfield name="STREAM" low="8" high="9" type="uint"/>
+ <bitfield name="BLOCK_DMA_WITHIN_FRAME" pos="12" type="boolean"/>
<bitfield name="TE" pos="31" type="boolean"/>
</reg32>
<reg32 offset="0x0008c" name="TRIG_DMA"/>
@@ -130,12 +187,34 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<bitfield name="TX_EOT_APPEND" pos="0" type="boolean"/>
<bitfield name="RX_EOT_IGNORE" pos="4" type="boolean"/>
</reg32>
- <reg32 offset="0x000ac" name="LANE_SWAP_CTRL"/>
+ <reg32 offset="0x000ac" name="LANE_SWAP_CTRL">
+ <bitfield name="DLN_SWAP_SEL" low="0" high="2" type="dsi_lane_swap"/>
+ </reg32>
<reg32 offset="0x00108" name="ERR_INT_MASK0"/>
<reg32 offset="0x0010c" name="INTR_CTRL" type="DSI_IRQ"/>
<reg32 offset="0x00114" name="RESET"/>
- <reg32 offset="0x00118" name="CLK_CTRL"/>
- <reg32 offset="0x00128" name="PHY_RESET"/>
+ <reg32 offset="0x00118" name="CLK_CTRL">
+ <bitfield name="AHBS_HCLK_ON" pos="0" type="boolean"/>
+ <bitfield name="AHBM_SCLK_ON" pos="1" type="boolean"/>
+ <bitfield name="PCLK_ON" pos="2" type="boolean"/>
+ <bitfield name="DSICLK_ON" pos="3" type="boolean"/>
+ <bitfield name="BYTECLK_ON" pos="4" type="boolean"/>
+ <bitfield name="ESCCLK_ON" pos="5" type="boolean"/>
+ <bitfield name="FORCE_ON_DYN_AHBM_HCLK" pos="9" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0011c" name="CLK_STATUS">
+ <bitfield name="PLL_UNLOCKED" pos="16" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00128" name="PHY_RESET">
+ <bitfield name="RESET" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x001d0" name="RDBK_DATA_CTRL">
+ <bitfield name="COUNT" low="16" high="23" type="uint"/>
+ <bitfield name="CLR" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x001f0" name="VERSION">
+ <bitfield name="MAJOR" low="24" high="31" type="uint"/>
+ </reg32>

<reg32 offset="0x00200" name="PHY_PLL_CTRL_0">
<bitfield name="ENABLE" pos="0" type="boolean"/>
@@ -272,4 +351,95 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
</reg32>
</domain>

+<domain name="DSI_28nm_PHY" width="32">
+ <array offset="0x00000" name="LN" length="4" stride="0x40">
+ <reg32 offset="0x00" name="CFG_0"/>
+ <reg32 offset="0x04" name="CFG_1"/>
+ <reg32 offset="0x08" name="CFG_2"/>
+ <reg32 offset="0x0c" name="CFG_3"/>
+ <reg32 offset="0x10" name="CFG_4"/>
+ <reg32 offset="0x14" name="TEST_DATAPATH"/>
+ <reg32 offset="0x18" name="DEBUG_SEL"/>
+ <reg32 offset="0x1c" name="TEST_STR_0"/>
+ <reg32 offset="0x20" name="TEST_STR_1"/>
+ </array>
+
+ <reg32 offset="0x00100" name="LNCK_CFG_0"/>
+ <reg32 offset="0x00104" name="LNCK_CFG_1"/>
+ <reg32 offset="0x00108" name="LNCK_CFG_2"/>
+ <reg32 offset="0x0010c" name="LNCK_CFG_3"/>
+ <reg32 offset="0x00110" name="LNCK_CFG_4"/>
+ <reg32 offset="0x00114" name="LNCK_TEST_DATAPATH"/>
+ <reg32 offset="0x00118" name="LNCK_DEBUG_SEL"/>
+ <reg32 offset="0x0011c" name="LNCK_TEST_STR0"/>
+ <reg32 offset="0x00120" name="LNCK_TEST_STR1"/>
+
+ <reg32 offset="0x00140" name="TIMING_CTRL_0">
+ <bitfield name="CLK_ZERO" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00144" name="TIMING_CTRL_1">
+ <bitfield name="CLK_TRAIL" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00148" name="TIMING_CTRL_2">
+ <bitfield name="CLK_PREPARE" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0014c" name="TIMING_CTRL_3">
+ <bitfield name="CLK_ZERO_8" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00150" name="TIMING_CTRL_4">
+ <bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00154" name="TIMING_CTRL_5">
+ <bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00158" name="TIMING_CTRL_6">
+ <bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0015c" name="TIMING_CTRL_7">
+ <bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00160" name="TIMING_CTRL_8">
+ <bitfield name="HS_RQST" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00164" name="TIMING_CTRL_9">
+ <bitfield name="TA_GO" low="0" high="2" type="uint"/>
+ <bitfield name="TA_SURE" low="4" high="6" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00168" name="TIMING_CTRL_10">
+ <bitfield name="TA_GET" low="0" high="2" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0016c" name="TIMING_CTRL_11">
+ <bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/>
+ </reg32>
+
+ <reg32 offset="0x00170" name="CTRL_0"/>
+ <reg32 offset="0x00174" name="CTRL_1"/>
+ <reg32 offset="0x00178" name="CTRL_2"/>
+ <reg32 offset="0x0017c" name="CTRL_3"/>
+ <reg32 offset="0x00180" name="CTRL_4"/>
+
+ <reg32 offset="0x00184" name="STRENGTH_0"/>
+ <reg32 offset="0x00188" name="STRENGTH_1"/>
+
+ <reg32 offset="0x001b4" name="BIST_CTRL_0"/>
+ <reg32 offset="0x001b8" name="BIST_CTRL_1"/>
+ <reg32 offset="0x001bc" name="BIST_CTRL_2"/>
+ <reg32 offset="0x001c0" name="BIST_CTRL_3"/>
+ <reg32 offset="0x001c4" name="BIST_CTRL_4"/>
+ <reg32 offset="0x001c8" name="BIST_CTRL_5"/>
+
+ <reg32 offset="0x001d4" name="GLBL_TEST_CTRL"/>
+ <reg32 offset="0x001dc" name="LDO_CNTRL"/>
+</domain>
+
+<domain name="DSI_28nm_PHY_REGULATOR" width="32">
+ <reg32 offset="0x00000" name="CTRL_0"/>
+ <reg32 offset="0x00004" name="CTRL_1"/>
+ <reg32 offset="0x00008" name="CTRL_2"/>
+ <reg32 offset="0x0000c" name="CTRL_3"/>
+ <reg32 offset="0x00010" name="CTRL_4"/>
+ <reg32 offset="0x00014" name="CTRL_5"/>
+ <reg32 offset="0x00018" name="CAL_PWR_CFG"/>
+</domain>
+
</database>
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Next message: Hai Li: "[PATCH 0/4] drm/msm: Initial add DSI support"
Previous message: David Rientjes: "Re: [PATCH 01/32] do_fork(): Rename 'stack_size' argument to reflect actual use"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]