[RESEND 6/7] ARM: davinci: irqs: Correct McASP1 TX interrupt definition for DM646x

From: Peter Ujfalusi
Date: Thu Mar 12 2015 - 04:07:38 EST


McASP1 TX interrupt is 30, not 32 on DM646x DMSoC

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@xxxxxx>
---
arch/arm/mach-davinci/include/mach/irqs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index 354af71798dc..edb2ca62321a 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -129,8 +129,8 @@
#define IRQ_DM646X_EMACMISCINT 27
#define IRQ_DM646X_MCASP0TXINT 28
#define IRQ_DM646X_MCASP0RXINT 29
+#define IRQ_DM646X_MCASP1TXINT 30
#define IRQ_DM646X_RESERVED_3 31
-#define IRQ_DM646X_MCASP1TXINT 32
#define IRQ_DM646X_VLQINT 38
#define IRQ_DM646X_UARTINT2 42
#define IRQ_DM646X_SPINT0 43
--
2.3.0

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