Re: [PATCH] clk: fractional-divider: support for divider bypassing

[Mike Turquette]

Quoting Stephen Boyd (2015-02-02 11:42:55)
> On 02/02/15 05:37, Heikki Krogerus wrote:
> > If the divider or multiplier values values are 0 in the
> 
> s/values//
> 
> > register, bypassing the divider and returning the parent
> > clock rate in clk_fd_recalc_rate().
> >
> > Signed-off-by: Heikki Krogerus <heikki.krogerus@xxxxxxxxxxxxxxx>
> > ---
> 
> Reviewed-by: Stephen Boyd <sboyd@xxxxxxxxxxxxxx>

Applied to clk-next.

Regards,
Mike

> 
> >  drivers/clk/clk-fractional-divider.c | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
> > index dc91da7..34d6c51 100644
> > --- a/drivers/clk/clk-fractional-divider.c
> > +++ b/drivers/clk/clk-fractional-divider.c
> > @@ -36,6 +36,9 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
> >       m = (val & fd->mmask) >> fd->mshift;
> >       n = (val & fd->nmask) >> fd->nshift;
> >  
> > +     if (!n || !m)
> > +             return parent_rate;
> > +
> >       ret = (u64)parent_rate * m;
> >       do_div(ret, n);
> >  
> 
> 
> -- 
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 
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