Re: [PATCH 1/3] perf, x86: Add new cache events table for Haswell

[Andi Kleen]

> Just in case someone is crazy enough to run a 32bit kernel on HSW, this
> needs to be BIT_ULL() -- also for compile testing, gcc tends to complain
> about things like (1UL << 32) for ILP32 targets.

Ok.

> Now the other tables create little helpers like:
> 
> #define HSW_DMND_READ	(HSW_DMND_DATA_RD)
> #define HSW_DMND_WRITE	(HSW_DMND_RFO)
> 
> #define HSW_L3_ACCESS	(HSW_ANY_RESPONSE)
> #define HSW_L3_MISS	(HSW_L3_MISS)
> 
> And compose the tables values using those:
> 
> 	HSW_DMND_READ|HSW_L3_ACCESS
> 
> Please do so here too.

I'm trying to stay with the official documented bit names. No such bit names exist.
If we make up our own names nobody else can read it anymore.

> 
> Now; when comparing these value to the SNB for example I note that you
> include ANY_SNOOP and SUPPLIER_NONE in L3_ACCESS, SNB and other do not,
> please explain.

You're supposed to set a snoop and supplier qualifier.
AFAIK SNB should set them too. It may work without them due to some
quirk.

-Andi

-- 
ak@xxxxxxxxxxxxxxx -- Speaking for myself only
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