Re: [PATCH] KVM: x86: save a bit in the decoding flags

[Radim KrÄmÃÅ]

2014-11-06 18:46+0100, Paolo Bonzini:
> AVX instructions are just tweaks of the operand length and the alignment
> restrictions of SSE instructions, and in fact the Avx bit is just a
> duplicate of Unaligned.  Drop it.
> 
> Suggested-by: Nadav Amit <namit@xxxxxxxxxxxxxxxxx>
> Signed-off-by: Paolo Bonzini <pbonzini@xxxxxxxxxx>
> ---

I think this forces our future AVX implementation to be very hacky,
we couldn't tell explicitly (un)aligned SSE2/AVX apart.

>  arch/x86/kvm/emulate.c |    5 +----
>  1 files changed, 1 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
> index 9cc476f..87c9431 100644
> --- a/arch/x86/kvm/emulate.c
> +++ b/arch/x86/kvm/emulate.c
> @@ -157,7 +157,7 @@
>  #define Mmx         ((u64)1 << 40)  /* MMX Vector instruction */
>  #define Aligned     ((u64)1 << 41)  /* Explicitly aligned (e.g. MOVDQA) */
>  #define Unaligned   ((u64)1 << 42)  /* Explicitly unaligned (e.g. MOVDQU) */
> -#define Avx         ((u64)1 << 43)  /* Advanced Vector Extensions */
> +#define No16        ((u64)1 << 43)  /* No 16 bit operand */
>  #define Fastop      ((u64)1 << 44)  /* Use opcode::u.fastop */
>  #define NoWrite     ((u64)1 << 45)  /* No writeback */
>  #define SrcWrite    ((u64)1 << 46)  /* Write back src operand */
> @@ -167,7 +167,6 @@
>  #define NoBigReal   ((u64)1 << 50)  /* No big real mode */
>  #define PrivUD      ((u64)1 << 51)  /* #UD instead of #GP on CPL > 0 */
>  #define NearBranch  ((u64)1 << 52)  /* Near branches */
> -#define No16	    ((u64)1 << 53)  /* No 16 bit operand */
>  
>  #define DstXacc     (DstAccLo | SrcAccHi | SrcWrite)
>  
> @@ -646,8 +645,6 @@ static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
>  		return true;
>  	else if (ctxt->d & Unaligned)
>  		return false;
> -	else if (ctxt->d & Avx)
> -		return false;
>  	else
>  		return true;

(return !(ctxt->d & Unaligned);)

>  }
> -- 
> 1.7.1
> 
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