[PATCH] fixup! irqchip: gic: Support hierarchy irq domain.

[Marc Zyngier]

---
 drivers/irqchip/Kconfig   |  1 +
 drivers/irqchip/irq-gic.c | 53 ++++++++++++++++++++++---------------------=
----
 2 files changed, 26 insertions(+), 28 deletions(-)

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index b8632bf..2a48e0a 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -5,6 +5,7 @@ config IRQCHIP
 config ARM_GIC
 =09bool
 =09select IRQ_DOMAIN
+=09select IRQ_DOMAIN_HIERARCHY
 =09select MULTI_IRQ_HANDLER
=20
 config GIC_NON_BANKED
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 17f5aa6..a99c211 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -835,8 +835,6 @@ static struct notifier_block gic_cpu_notifier =3D {
 };
 #endif
=20
-
-#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int vi=
rq,
 =09=09=09=09unsigned int nr_irqs, void *arg)
 {
@@ -870,10 +868,8 @@ static void gic_irq_domain_free(struct irq_domain *dom=
ain, unsigned int virq,
 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops =3D {
 =09.alloc =3D gic_irq_domain_alloc,
 =09.free =3D gic_irq_domain_free,
+=09.xlate =3D gic_irq_domain_xlate,
 };
-#else
-#define gic_irq_domain_hierarchy_ops 0
-#endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */
=20
 static const struct irq_domain_ops gic_irq_domain_ops =3D {
 =09.map =3D gic_irq_domain_map,
@@ -965,18 +961,6 @@ void __init gic_init_bases(unsigned int gic_nr, int ir=
q_start,
 =09=09gic_cpu_map[i] =3D 0xff;
=20
 =09/*
-=09 * For primary GICs, skip over SGIs.
-=09 * For secondary GICs, skip over PPIs, too.
-=09 */
-=09if (gic_nr =3D=3D 0 && (irq_start & 31) > 0) {
-=09=09hwirq_base =3D 16;
-=09=09if (irq_start !=3D -1)
-=09=09=09irq_start =3D (irq_start & ~31) + 16;
-=09} else {
-=09=09hwirq_base =3D 32;
-=09}
-
-=09/*
 =09 * Find out how many interrupts are supported.
 =09 * The GIC only supports up to 1020 interrupt sources.
 =09 */
@@ -986,14 +970,31 @@ void __init gic_init_bases(unsigned int gic_nr, int i=
rq_start,
 =09=09gic_irqs =3D 1020;
 =09gic->gic_irqs =3D gic_irqs;
=20
-=09gic_irqs -=3D hwirq_base; /* calculate # of irqs to allocate */
+=09if (node) {=09=09/* DT case */
+=09=09const struct irq_domain_ops *ops =3D &gic_irq_domain_hierarchy_ops;
+
+=09=09if (!of_property_read_u32(node, "arm,routable-irqs",
+=09=09=09=09=09  &nr_routable_irqs)) {
+=09=09=09ops =3D &gic_irq_domain_ops;
+=09=09=09gic_irqs =3D nr_routable_irqs;
+=09=09}
+
+=09=09gic->domain =3D irq_domain_add_linear(node, gic_irqs, ops, gic);
+=09} else {=09=09/* Non-DT case */
+=09=09/*
+=09=09 * For primary GICs, skip over SGIs.
+=09=09 * For secondary GICs, skip over PPIs, too.
+=09=09 */
+=09=09if (gic_nr =3D=3D 0 && (irq_start & 31) > 0) {
+=09=09=09hwirq_base =3D 16;
+=09=09=09if (irq_start !=3D -1)
+=09=09=09=09irq_start =3D (irq_start & ~31) + 16;
+=09=09} else {
+=09=09=09hwirq_base =3D 32;
+=09=09}
+
+=09=09gic_irqs -=3D hwirq_base; /* calculate # of irqs to allocate */
=20
-=09if (IS_ENABLED(CONFIG_IRQ_DOMAIN_HIERARCHY) &&
-=09=09of_find_property(node, "arm,irq-domain-hierarchy", NULL))
-=09=09gic->domain =3D irq_domain_add_linear(node, gic_irqs,
-=09=09=09=09=09&gic_irq_domain_hierarchy_ops, gic);
-=09else if (of_property_read_u32(node, "arm,routable-irqs",
-=09=09=09=09 &nr_routable_irqs)) {
 =09=09irq_base =3D irq_alloc_descs(irq_start, 16, gic_irqs,
 =09=09=09=09=09   numa_node_id());
 =09=09if (IS_ERR_VALUE(irq_base)) {
@@ -1004,10 +1005,6 @@ void __init gic_init_bases(unsigned int gic_nr, int =
irq_start,
=20
 =09=09gic->domain =3D irq_domain_add_legacy(node, gic_irqs, irq_base,
 =09=09=09=09=09hwirq_base, &gic_irq_domain_ops, gic);
-=09} else {
-=09=09gic->domain =3D irq_domain_add_linear(node, nr_routable_irqs,
-=09=09=09=09=09=09    &gic_irq_domain_ops,
-=09=09=09=09=09=09    gic);
 =09}
=20
 =09if (WARN_ON(!gic->domain))
--=20
2.0.4

--------------030407050101090003060102--

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