Re: [PATCH v4 00/22] perf: Add infrastructure and support for Intel PT

[Peter Zijlstra]

On Tue, Sep 02, 2014 at 02:18:16PM -0600, Mathieu Poirier wrote:
> Pawell, many thanks for looping me in.
> 
> I am definitely not a perf-internal guru and as such won't be able to
> comment on the implementation.  On the flip side it is easy for me to see
> how the work on coresight done at Linaro can be made to tie-in what
> Alexander is proposing.  Albeit not at the top of the priority list at this
> time, integration with perf (and ftrace) is definitely on the roadmap.
> 
> Powell is correct in his statement that Linaro's work in HW trace decoding
> is (currently) mainly focused on processor tracing but that will change
> when we have the basic infrastructure upstreamed.
> 
> Last but not least it would be interesting to have more information on the
> "sideband data".  With coresight we have something called "metadata", also
> related to how the trace source was configured and instrumental to proper
> trace decoding.  I'm pretty sure we are facing the same problems.

So we use the sideband or AUX data stream to export the 'big' data
stream generated by the CPU in an opaque manner. For every AUX data
block 'posted' we issue an event into the regular data buffer that
describes it.

I was assuming that both ARM and MIPS would generate a single data
stream as well. So please do tell more about your meta-data; is that a
one time thing or a second continuous stream of data, albeit smaller
than the main stream?

The way I read your explanation it is a one time blob generated once you
setup the hardware. I suppose we could either dump it once into the
normal data stream or maybe dump it once every time we generate an AUX
buffer event into the normal data stream -- if its not too big.

In any case, can you point us to public documentation of the ARM
CoreSight stuff and maybe provide a short summary for the tl;dr crowd?
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