Re: [PATCH] clk: qcom: Fix sdc 144kHz frequency entry

[Stephen Boyd]

On 09/02/14 14:44, Mike Turquette wrote:
> Quoting Stephen Boyd (2014-08-29 12:49:26)
>> The pre-divider for the sdc clocks only has 2 bits in it, so we
>> can't possibly divide by anything larger than 4 here.
>> Furthermore, we program the value of ~(n - m) and the n value is
>> larger than 8 bits (max of 256). Replace this entry with 200kHz
>> which is close enough to 144kHz to be usable.
>>
>> Cc: Kumar Gala <galak@xxxxxxxxxxxxxx>
>> Cc: Andy Gross <agross@xxxxxxxxxxxxxx>
>> Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)"
>> Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxxxxxx>
> Do you need this pulled into a 3.17-rc?
>

Yes that would be helpful since this fixes a driver introduced into 3.17.

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