Re: [PATCH v3 4/4] can: flexcan: add vf610 support for FlexCAN
From: Stefan Agner
Date: Fri Jul 25 2014 - 06:50:42 EST
Am 2014-07-16 08:43, schrieb Stefan Agner:
> Am 2014-07-15 16:24, schrieb Marc Kleine-Budde:
> <snip>
>>> @@ -150,18 +171,20 @@
>>> * FLEXCAN hardware feature flags
>>> *
>>> * Below is some version info we got:
>>> - * SOC Version IP-Version Glitch- [TR]WRN_INT
>>> - * Filter? connected?
>>> - * MX25 FlexCAN2 03.00.00.00 no no
>>> - * MX28 FlexCAN2 03.00.04.00 yes yes
>>> - * MX35 FlexCAN2 03.00.00.00 no no
>>> - * MX53 FlexCAN2 03.00.00.00 yes no
>>> - * MX6s FlexCAN3 10.00.12.00 yes yes
>>> + * SOC Version IP-Version Glitch- [TR]WRN_INT Memory err
>>> + * Filter? connected? detection
>>> + * MX25 FlexCAN2 03.00.00.00 no no no
>>> + * MX28 FlexCAN2 03.00.04.00 yes yes no
>>> + * MX35 FlexCAN2 03.00.00.00 no no no
>>> + * MX53 FlexCAN2 03.00.00.00 yes no no
>>> + * MX6s FlexCAN3 10.00.12.00 yes yes no
>>> + * VF610 FlexCAN3 ? no no yes
>> ^^ ^^
>>
>> Can you check the datasheet if the flexcan core has a "Glitch Filter
>> Width Register (FLEXCANx_GFWR)"
>
>
> There is no such register called GFWR/Glitch Filter or similar.
>
>> Can you check if the core generates a warning interrupt with the current
>> setup, if you don't switch on bus error reporting? This means internally
>> the [TR]WRN_INT is connected and works as specified.
>
> Ok, so I disabled TWRNMSK (Bit 11) in the control register and printed
> out the error and status register (ESR1), this is what I get:
> [ 191.285295] flexcan_irq, esr=00040080
> [ 191.288996] flexcan_irq, ctrl=17092051
>
> Bit 17 (TWRNINT) is not set while TWRNMSK is disabled. Hence [TR]WRN_INT
> is not connected?
Ping. Anything open/to do from my side?
--
Stefan
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