Re: [PATCH 08/19] perf c2c: Shared data analyser

[Peter Zijlstra]

On Mon, Mar 03, 2014 at 10:36:25PM +0100, Andi Kleen wrote:
> > Heh.  I never thought about that.  And sure enough a quick test with
> > mem-stores commented out produced the same results (minus the stores).
> > 
> > One would just have to 'figure' out what cacheline offsets are causing the
> > HITMs.
> 
> Often that can be determined statically from the instruction (register-offset)
> 
> However keep in mind that there is some skid so the instruction may not
> be correct.

Even with the real_ip pebs field? I thought the whole purpose of that
was to tag the actual instruction matching the event.
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