Re: Tegra clockframework fixes for 3.14

[Peter De Schrijver]

Mike,

> On Mon, Feb 24, 2014 at 02:02:11AM +0100, Mike Turquette wrote:
> > Quoting Peter De Schrijver (2014-02-20 09:27:44)
> > > Hi Mike,
> > > 
> > > Could you merge these fixes still for 3.14?
> > 
> > No problem, but can you provide a list of the regressions fixed? I'll
> > add those to my merge commit message. No need for you to respin
> > anything. Next time if you could submit a signed tag with the
> > regressions listed in the message it would be a great help.
> > 
> 
> This fixes the following issues:
> 
> clk: tegra124: remove gr2d and gr3d clocks - accesses to undefined registers
> clk: tegra: Fix vic03 mux index - wrong parent when PLLC3 is selected (because clk_m is actually selected)
> clk: tegra: use max divider if divider overflows - make tegra fractional divider match the clk-div.c behaviour
> clk: tegra: cclk_lp has a pllx/2 divider - pllx runs at half the programmed rate
> clk: tegra: fix sdmmc clks on Tegra1x4 - wrong parent selection
> clk: tegra: fix host1x clock on Tegra124 - wrong parent selection
> clk: tegra: PLLD2 fixes for hdmi - PLL runs at wrong rate
> clk: tegra: Fix PLLD mnp table - PLL runs at wrong rate
> clk: tegra: Fix PLLP rate table - kernel panic when using coreboot
> clk: tegra: Correct clock number for UARTE - wrong clock when using UARTE
> clk: tegra: Add missing Tegra20 fuse clks - fuse driver broken
> 

Is this ok for you?

Thanks,

Peter.
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